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authorDave Airlie <airlied@redhat.com>2014-05-01 21:05:21 -0400
committerDave Airlie <airlied@redhat.com>2014-05-23 07:04:08 -0400
commit3c8a0922e0b774aa394a6925f11976ccfc852808 (patch)
tree6adccbe1471a451aa569ea37181248b403c5696a /include/drm/drm_dp_helper.h
parent263432b021cd252570001c10404367e948ac10f0 (diff)
drm/dp_helper: add defines for DP 1.2 and MST support. (v2)
This just adds the defines from the DP 1.2 spec, which we will use later. fix some DP MST to 1.2 MST Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Todd Previte <tprevite@gmail.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Diffstat (limited to 'include/drm/drm_dp_helper.h')
-rw-r--r--include/drm/drm_dp_helper.h78
1 files changed, 78 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index cfcacec5b89d..c8857e6159a5 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -37,6 +37,7 @@
37 * eDP: Embedded DisplayPort version 1 37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a 38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2 39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
40 * 41 *
41 * 1.2 formally includes both eDP and DPI definitions. 42 * 1.2 formally includes both eDP and DPI definitions.
42 */ 43 */
@@ -103,9 +104,14 @@
103#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 104#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
104 105
105/* Multiple stream transport */ 106/* Multiple stream transport */
107#define DP_FAUX_CAP 0x020 /* 1.2 */
108# define DP_FAUX_CAP_1 (1 << 0)
109
106#define DP_MSTM_CAP 0x021 /* 1.2 */ 110#define DP_MSTM_CAP 0x021 /* 1.2 */
107# define DP_MST_CAP (1 << 0) 111# define DP_MST_CAP (1 << 0)
108 112
113#define DP_GUID 0x030 /* 1.2 */
114
109#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 115#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
110# define DP_PSR_IS_SUPPORTED 1 116# define DP_PSR_IS_SUPPORTED 1
111#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 117#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
@@ -221,6 +227,16 @@
221# define DP_PSR_CRC_VERIFICATION (1 << 2) 227# define DP_PSR_CRC_VERIFICATION (1 << 2)
222# define DP_PSR_FRAME_CAPTURE (1 << 3) 228# define DP_PSR_FRAME_CAPTURE (1 << 3)
223 229
230#define DP_ADAPTER_CTRL 0x1a0
231# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
232
233#define DP_BRANCH_DEVICE_CTRL 0x1a1
234# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
235
236#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
237#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
238#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
239
224#define DP_SINK_COUNT 0x200 240#define DP_SINK_COUNT 0x200
225/* prior to 1.2 bit 7 was reserved mbz */ 241/* prior to 1.2 bit 7 was reserved mbz */
226# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 242# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
@@ -230,6 +246,9 @@
230# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 246# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
231# define DP_AUTOMATED_TEST_REQUEST (1 << 1) 247# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
232# define DP_CP_IRQ (1 << 2) 248# define DP_CP_IRQ (1 << 2)
249# define DP_MCCS_IRQ (1 << 3)
250# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
251# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
233# define DP_SINK_SPECIFIC_IRQ (1 << 6) 252# define DP_SINK_SPECIFIC_IRQ (1 << 6)
234 253
235#define DP_LANE0_1_STATUS 0x202 254#define DP_LANE0_1_STATUS 0x202
@@ -294,6 +313,13 @@
294#define DP_TEST_SINK 0x270 313#define DP_TEST_SINK 0x270
295#define DP_TEST_SINK_START (1 << 0) 314#define DP_TEST_SINK_START (1 << 0)
296 315
316#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
317# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
318# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
319
320#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
321/* up to ID_SLOT_63 at 0x2ff */
322
297#define DP_SOURCE_OUI 0x300 323#define DP_SOURCE_OUI 0x300
298#define DP_SINK_OUI 0x400 324#define DP_SINK_OUI 0x400
299#define DP_BRANCH_OUI 0x500 325#define DP_BRANCH_OUI 0x500
@@ -303,6 +329,21 @@
303# define DP_SET_POWER_D3 0x2 329# define DP_SET_POWER_D3 0x2
304# define DP_SET_POWER_MASK 0x3 330# define DP_SET_POWER_MASK 0x3
305 331
332#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
333#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
334#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
335#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
336
337#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
338/* 0-5 sink count */
339# define DP_SINK_COUNT_CP_READY (1 << 6)
340
341#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
342
343#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
344
345#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
346
306#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 347#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
307# define DP_PSR_LINK_CRC_ERROR (1 << 0) 348# define DP_PSR_LINK_CRC_ERROR (1 << 0)
308# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 349# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
@@ -319,6 +360,43 @@
319# define DP_PSR_SINK_INTERNAL_ERROR 7 360# define DP_PSR_SINK_INTERNAL_ERROR 7
320# define DP_PSR_SINK_STATE_MASK 0x07 361# define DP_PSR_SINK_STATE_MASK 0x07
321 362
363/* DP 1.2 Sideband message defines */
364/* peer device type - DP 1.2a Table 2-92 */
365#define DP_PEER_DEVICE_NONE 0x0
366#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
367#define DP_PEER_DEVICE_MST_BRANCHING 0x2
368#define DP_PEER_DEVICE_SST_SINK 0x3
369#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
370
371/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
372#define DP_LINK_ADDRESS 0x01
373#define DP_CONNECTION_STATUS_NOTIFY 0x02
374#define DP_ENUM_PATH_RESOURCES 0x10
375#define DP_ALLOCATE_PAYLOAD 0x11
376#define DP_QUERY_PAYLOAD 0x12
377#define DP_RESOURCE_STATUS_NOTIFY 0x13
378#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
379#define DP_REMOTE_DPCD_READ 0x20
380#define DP_REMOTE_DPCD_WRITE 0x21
381#define DP_REMOTE_I2C_READ 0x22
382#define DP_REMOTE_I2C_WRITE 0x23
383#define DP_POWER_UP_PHY 0x24
384#define DP_POWER_DOWN_PHY 0x25
385#define DP_SINK_EVENT_NOTIFY 0x30
386#define DP_QUERY_STREAM_ENC_STATUS 0x38
387
388/* DP 1.2 MST sideband nak reasons - table 2.84 */
389#define DP_NAK_WRITE_FAILURE 0x01
390#define DP_NAK_INVALID_READ 0x02
391#define DP_NAK_CRC_FAILURE 0x03
392#define DP_NAK_BAD_PARAM 0x04
393#define DP_NAK_DEFER 0x05
394#define DP_NAK_LINK_FAILURE 0x06
395#define DP_NAK_NO_RESOURCES 0x07
396#define DP_NAK_DPCD_FAIL 0x08
397#define DP_NAK_I2C_NAK 0x09
398#define DP_NAK_ALLOCATE_FAIL 0x0a
399
322#define MODE_I2C_START 1 400#define MODE_I2C_START 1
323#define MODE_I2C_WRITE 2 401#define MODE_I2C_WRITE 2
324#define MODE_I2C_READ 4 402#define MODE_I2C_READ 4