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authorJerome Glisse <jglisse@redhat.com>2012-06-09 10:57:41 -0400
committerDave Airlie <airlied@redhat.com>2012-06-10 12:41:46 -0400
commitd26098759cf6d32148649c165f87a7590bc25b89 (patch)
tree3aa9fabc265004a096e9a67044604f4dfd174717 /include/drm/drm_crtc.h
parentcfaf025112d3856637ff34a767ef785ef5cf2ca9 (diff)
drm/radeon: fix tiling and command stream checking on evergreen v3
Fix regresson since the introduction of command stream checking on evergreen (thread referenced below). Issue is cause by ddx allocating bo with formula width*height*bpp while programming the GPU command stream with ALIGN(height, 8). In some case (where page alignment does not hide the extra size bo should be according to height alignment) the kernel will reject the command stream. This patch reprogram the command stream to slice - 1 (slice is a derivative value from height) which avoid rejecting the command stream while keeping the value of command stream checking from a security point of view. This patch also fix wrong computation of layer size for 2D tiled surface. Which should fix issue when 2D color tiling is enabled. This dump the radeon KMS_DRIVER_MINOR so userspace can know if they are on a fixed kernel or not. https://lkml.org/lkml/2012/6/3/80 https://bugs.freedesktop.org/show_bug.cgi?id=50892 https://bugs.freedesktop.org/show_bug.cgi?id=50857 !!! STABLE need a custom version of this patch for 3.4 !!! v2: actually bump the minor version and add comment about stable v3: do compute the height the ddx was trying to use [airlied: drop left over debug] Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/drm/drm_crtc.h')
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