aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-xtensa/sigcontext.h
diff options
context:
space:
mode:
authorChris Zankel <chris@zankel.net>2007-05-31 20:49:32 -0400
committerChris Zankel <chris@zankel.net>2007-05-31 20:49:32 -0400
commit29c4dfd92edc26c2cd2c0c64c9201d5b91d6418e (patch)
tree64b2884bb49a86f2895d9206b79bf9f64e384615 /include/asm-xtensa/sigcontext.h
parentadba09f01577ea441a761a85aacb1e43b58d35c4 (diff)
[XTENSA] Remove non-rt signal handling
The non-rt signal handling was never really used, so we don't break anything. This patch also cleans up the signal stack-frame to make it independent from the processor configuration. It also improves the method used for controlling single-stepping. We now save and restore the 'icountlevel' register that controls single stepping and set or clear the saved state to enable or disable it. Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'include/asm-xtensa/sigcontext.h')
-rw-r--r--include/asm-xtensa/sigcontext.h24
1 files changed, 5 insertions, 19 deletions
diff --git a/include/asm-xtensa/sigcontext.h b/include/asm-xtensa/sigcontext.h
index a75177291418..e3381cee5059 100644
--- a/include/asm-xtensa/sigcontext.h
+++ b/include/asm-xtensa/sigcontext.h
@@ -5,21 +5,12 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 2001 - 2003 Tensilica Inc. 8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */ 9 */
10 10
11#ifndef _XTENSA_SIGCONTEXT_H 11#ifndef _XTENSA_SIGCONTEXT_H
12#define _XTENSA_SIGCONTEXT_H 12#define _XTENSA_SIGCONTEXT_H
13 13
14#define _ASMLANGUAGE
15#include <asm/processor.h>
16#include <asm/coprocessor.h>
17
18
19struct _cpstate {
20 unsigned char _cpstate[XTENSA_CP_EXTRA_SIZE];
21} __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
22
23 14
24struct sigcontext { 15struct sigcontext {
25 unsigned long oldmask; 16 unsigned long oldmask;
@@ -27,18 +18,13 @@ struct sigcontext {
27 /* CPU registers */ 18 /* CPU registers */
28 unsigned long sc_pc; 19 unsigned long sc_pc;
29 unsigned long sc_ps; 20 unsigned long sc_ps;
30 unsigned long sc_wmask;
31 unsigned long sc_windowbase;
32 unsigned long sc_windowstart;
33 unsigned long sc_lbeg; 21 unsigned long sc_lbeg;
34 unsigned long sc_lend; 22 unsigned long sc_lend;
35 unsigned long sc_lcount; 23 unsigned long sc_lcount;
36 unsigned long sc_sar; 24 unsigned long sc_sar;
37 unsigned long sc_depc; 25 unsigned long sc_acclo;
38 unsigned long sc_dareg0; 26 unsigned long sc_acchi;
39 unsigned long sc_treg[4]; 27 unsigned long sc_a[16];
40 unsigned long sc_areg[XCHAL_NUM_AREGS];
41 struct _cpstate *sc_cpstate;
42}; 28};
43 29
44#endif /* __ASM_XTENSA_SIGCONTEXT_H */ 30#endif /* _XTENSA_SIGCONTEXT_H */