[XTENSA] Add support for configurable registers and coprocessors

The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.

This patch adds support for these additional states:

- save and restore registers that are used by the compiler upon
  interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf

Signed-off-by: Chris Zankel <chris@zankel.net>

1 files changed, 8 insertions, 1 deletions

diff --git a/include/asm-xtensa/regs.h b/include/asm-xtensa/regs.h
index c913d259faaa..d4baed246928 100644
--- a/include/asm-xtensa/regs.h
+++ b/include/asm-xtensa/regs.h
@@ -100,7 +100,14 @@
 #define EXCCAUSE_DTLB_SIZE_RESTRICTION          27
 #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE           28
 #define EXCCAUSE_STORE_CACHE_ATTRIBUTE          29
-#define EXCCAUSE_FLOATING_POINT                 40
+#define EXCCAUSE_COPROCESSOR0_DISABLED          32
+#define EXCCAUSE_COPROCESSOR1_DISABLED          33
+#define EXCCAUSE_COPROCESSOR2_DISABLED          34
+#define EXCCAUSE_COPROCESSOR3_DISABLED          35
+#define EXCCAUSE_COPROCESSOR4_DISABLED          36
+#define EXCCAUSE_COPROCESSOR5_DISABLED          37
+#define EXCCAUSE_COPROCESSOR6_DISABLED          38
+#define EXCCAUSE_COPROCESSOR7_DISABLED          39
 
 /*  PS register fields.  */