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authorChris Zankel <czankel@tensilica.com>2006-12-10 05:18:48 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-10 12:55:39 -0500
commit173d6681380aa1d60dfc35ed7178bd7811ba2784 (patch)
tree9d6d4d2c6dd791499ebab558647efb67ac88ae3a /include/asm-xtensa/pgtable.h
parentfd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0 (diff)
[PATCH] xtensa: remove extra header files
The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-xtensa/pgtable.h')
-rw-r--r--include/asm-xtensa/pgtable.h41
1 files changed, 1 insertions, 40 deletions
diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h
index b4318934b10d..2d4b5db6ea63 100644
--- a/include/asm-xtensa/pgtable.h
+++ b/include/asm-xtensa/pgtable.h
@@ -14,45 +14,6 @@
14#include <asm-generic/pgtable-nopmd.h> 14#include <asm-generic/pgtable-nopmd.h>
15#include <asm/page.h> 15#include <asm/page.h>
16 16
17/* Assertions. */
18
19#ifdef CONFIG_MMU
20
21
22#if (XCHAL_MMU_RINGS < 2)
23# error Linux build assumes at least 2 ring levels.
24#endif
25
26#if (XCHAL_MMU_CA_BITS != 4)
27# error We assume exactly four bits for CA.
28#endif
29
30#if (XCHAL_MMU_SR_BITS != 0)
31# error We have no room for SR bits.
32#endif
33
34/*
35 * Use the first min-wired way for mapping page-table pages.
36 * Page coloring requires a second min-wired way.
37 */
38
39#if (XCHAL_DTLB_MINWIRED_SETS == 0)
40# error Need a min-wired way for mapping page-table pages
41#endif
42
43#define DTLB_WAY_PGTABLE XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAY)
44
45#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
46# if XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAYS) >= 2
47# define DTLB_WAY_DCACHE_ALIAS0 (DTLB_WAY_PGTABLE + 1)
48# define DTLB_WAY_DCACHE_ALIAS1 (DTLB_WAY_PGTABLE + 2)
49# else
50# error Page coloring requires its own wired dtlb way!
51# endif
52#endif
53
54#endif /* CONFIG_MMU */
55
56/* 17/*
57 * We only use two ring levels, user and kernel space. 18 * We only use two ring levels, user and kernel space.
58 */ 19 */
@@ -97,7 +58,7 @@
97#define PGD_ORDER 0 58#define PGD_ORDER 0
98#define PMD_ORDER 0 59#define PMD_ORDER 0
99#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 60#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
100#define FIRST_USER_ADDRESS XCHAL_SEG_MAPPABLE_VADDR 61#define FIRST_USER_ADDRESS 0
101#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) 62#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
102 63
103/* virtual memory area. We keep a distance to other memory regions to be 64/* virtual memory area. We keep a distance to other memory regions to be