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authorChris Zankel <chris@zankel.net>2008-11-06 09:40:46 -0500
committerChris Zankel <chris@zankel.net>2008-11-06 13:25:09 -0500
commit367b8112fe2ea5c39a7bb4d263dcdd9b612fae18 (patch)
tree9f3349189718dd2c5678faf0ab38f389786b6925 /include/asm-xtensa/cache.h
parent206ead28377fee86b129637edada8c77816cc0d6 (diff)
xtensa: move headers files to arch/xtensa/include
Move all header files for xtensa to arch/xtensa/include and platform and variant header files to the appropriate arch/xtensa/platforms/ and arch/xtensa/variants/ directories. Moving the files gets also rid of all uses of symlinks in the Makefile. This has been completed already for the majority of the architectures and xtensa is one out of six missing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'include/asm-xtensa/cache.h')
-rw-r--r--include/asm-xtensa/cache.h33
1 files changed, 0 insertions, 33 deletions
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h
deleted file mode 100644
index 3bba2a540cf0..000000000000
--- a/include/asm-xtensa/cache.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * include/asm-xtensa/cache.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CACHE_H
12#define _XTENSA_CACHE_H
13
14#include <asm/variant/core.h>
15
16#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
17#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE
18#define SMP_CACHE_BYTES L1_CACHE_BYTES
19
20#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
21#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
22#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
23#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
24
25/* Maximum cache size per way. */
26#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
27# define CACHE_WAY_SIZE DCACHE_WAY_SIZE
28#else
29# define CACHE_WAY_SIZE ICACHE_WAY_SIZE
30#endif
31
32
33#endif /* _XTENSA_CACHE_H */