diff options
| author | Chris Zankel <czankel@tensilica.com> | 2006-12-10 05:18:47 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-10 12:55:39 -0500 |
| commit | fd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0 (patch) | |
| tree | 5225910274cbf362143a80b95b6b38c4a7d22e6d /include/asm-xtensa/byteorder.h | |
| parent | 5fcf7bb73f66cc1c4ad90788b0f367c4d6852b75 (diff) | |
[PATCH] xtensa: fix irq and misc fixes
Update the architecture specific interrupt handling code for Xtensa to support
the new API. Use generic BUG macros in bug.h, and some minor fixes.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-xtensa/byteorder.h')
| -rw-r--r-- | include/asm-xtensa/byteorder.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h index 0b1552569aae..0ba72ddbf889 100644 --- a/include/asm-xtensa/byteorder.h +++ b/include/asm-xtensa/byteorder.h | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | #include <asm/processor.h> | 14 | #include <asm/processor.h> |
| 15 | #include <asm/types.h> | 15 | #include <asm/types.h> |
| 16 | 16 | ||
| 17 | static __inline__ __const__ __u32 ___arch__swab32(__u32 x) | 17 | static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) |
| 18 | { | 18 | { |
| 19 | __u32 res; | 19 | __u32 res; |
| 20 | /* instruction sequence from Xtensa ISA release 2/2000 */ | 20 | /* instruction sequence from Xtensa ISA release 2/2000 */ |
| @@ -29,7 +29,7 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 x) | |||
| 29 | return res; | 29 | return res; |
| 30 | } | 30 | } |
| 31 | 31 | ||
| 32 | static __inline__ __const__ __u16 ___arch__swab16(__u16 x) | 32 | static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) |
| 33 | { | 33 | { |
| 34 | /* Given that 'short' values are signed (i.e., can be negative), | 34 | /* Given that 'short' values are signed (i.e., can be negative), |
| 35 | * we cannot assume that the upper 16-bits of the register are | 35 | * we cannot assume that the upper 16-bits of the register are |