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authorEric W. Biederman <ebiederm@xmission.com>2007-02-23 06:40:58 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-26 13:34:08 -0500
commit610142927b5bc149da92b03c7ab08b8b5f205b74 (patch)
tree600c115072fc5f28c07dddfbe52f0dcf376d8504 /include/asm-x86_64
parentbc5e81a1519abc69472bb67deace7bb1ac09d65a (diff)
[PATCH] x86_64 irq: Safely cleanup an irq after moving it.
The problem: After moving an interrupt when is it safe to teardown the data structures for receiving the interrupt at the old location? With a normal pci device it is possible to issue a read to a device to flush all posted writes. This does not work for the oldest ioapics because they are on a 3-wire apic bus which is a completely different data path. For some more modern ioapics when everything is using front side bus delivery you can flush interrupts by simply issuing a read to the ioapic. For other modern ioapics emperical testing has shown that this does not work. So it appears the only reliable way to know the last of the irqs from an ioapic have been received from before the ioapic was reprogrammed is to received the first irq from the ioapic from after it was reprogrammed. Once we know the last irq message has been received from an ioapic into a local apic we then need to know that irq message has been processed through the local apics. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-x86_64')
-rw-r--r--include/asm-x86_64/hw_irq.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/include/asm-x86_64/hw_irq.h b/include/asm-x86_64/hw_irq.h
index dc395edc2f2a..2e4b7a5ed1c4 100644
--- a/include/asm-x86_64/hw_irq.h
+++ b/include/asm-x86_64/hw_irq.h
@@ -32,10 +32,15 @@
32#define IA32_SYSCALL_VECTOR 0x80 32#define IA32_SYSCALL_VECTOR 0x80
33 33
34 34
35/* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
36 * cleanup after irq migration.
37 */
38#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
39
35/* 40/*
36 * Vectors 0x20-0x2f are used for ISA interrupts. 41 * Vectors 0x20-0x2f are used for ISA interrupts.
37 */ 42 */
38#define IRQ0_VECTOR FIRST_EXTERNAL_VECTOR 43#define IRQ0_VECTOR FIRST_EXTERNAL_VECTOR + 0x10
39#define IRQ1_VECTOR IRQ0_VECTOR + 1 44#define IRQ1_VECTOR IRQ0_VECTOR + 1
40#define IRQ2_VECTOR IRQ0_VECTOR + 2 45#define IRQ2_VECTOR IRQ0_VECTOR + 2
41#define IRQ3_VECTOR IRQ0_VECTOR + 3 46#define IRQ3_VECTOR IRQ0_VECTOR + 3
@@ -82,7 +87,7 @@
82 87
83/* 88/*
84 * First APIC vector available to drivers: (vectors 0x30-0xee) 89 * First APIC vector available to drivers: (vectors 0x30-0xee)
85 * we start at 0x31 to spread out vectors evenly between priority 90 * we start at 0x41 to spread out vectors evenly between priority
86 * levels. (0x80 is the syscall vector) 91 * levels. (0x80 is the syscall vector)
87 */ 92 */
88#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2) 93#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)