aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-x86_64
diff options
context:
space:
mode:
authorEric W. Biederman <ebiederm@xmission.com>2006-10-08 09:47:55 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-08 15:24:02 -0400
commitc7111c1318ee8890f385813f232fdb32643e2653 (patch)
treee21f8ee81f45f0c127a6233ed77d8052615d1fc8 /include/asm-x86_64
parentb940d22d58c41b2ae491dca9232850f6f38f3653 (diff)
[PATCH] x86_64 irq: Allocate a vector across all cpus for genapic_flat.
The problem we can't take advantage of lowest priority delivery mode if the vectors are allocated for only one cpu at a time. Nor can we work around hardware that assumes lowest priority delivery mode is always used with several cpus. So this patch introduces the concept of a vector_allocation_domain. A set of cpus that will receive an irq on the same vector. Currently the code for implementing this is placed in the genapic structure so we can vary this depending on how we are using the io_apics. This allows us to restore the previous behaviour of genapic_flat without removing the benefits of having separate vector allocation for large machines. This should also fix the problem report where a hyperthreaded cpu was receving the irq on the wrong hyperthread when in logical delivery mode because the previous behaviour is restored. This patch properly records our allocation of the first 16 irqs to the first 16 available vectors on all cpus. This should be fine but it may run into problems with multiple interrupts at the same interrupt level. Except for some badly maintained comments in the code and the behaviour of the interrupt allocator I have no real understanding of that problem. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64')
-rw-r--r--include/asm-x86_64/genapic.h1
-rw-r--r--include/asm-x86_64/mach_apic.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-x86_64/genapic.h b/include/asm-x86_64/genapic.h
index 81e714665344..a0e9a4b93484 100644
--- a/include/asm-x86_64/genapic.h
+++ b/include/asm-x86_64/genapic.h
@@ -18,6 +18,7 @@ struct genapic {
18 u32 int_dest_mode; 18 u32 int_dest_mode;
19 int (*apic_id_registered)(void); 19 int (*apic_id_registered)(void);
20 cpumask_t (*target_cpus)(void); 20 cpumask_t (*target_cpus)(void);
21 cpumask_t (*vector_allocation_domain)(int cpu);
21 void (*init_apic_ldr)(void); 22 void (*init_apic_ldr)(void);
22 /* ipi */ 23 /* ipi */
23 void (*send_IPI_mask)(cpumask_t mask, int vector); 24 void (*send_IPI_mask)(cpumask_t mask, int vector);
diff --git a/include/asm-x86_64/mach_apic.h b/include/asm-x86_64/mach_apic.h
index d33422450c00..7b7115a0c1c9 100644
--- a/include/asm-x86_64/mach_apic.h
+++ b/include/asm-x86_64/mach_apic.h
@@ -17,6 +17,7 @@
17#define INT_DELIVERY_MODE (genapic->int_delivery_mode) 17#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
18#define INT_DEST_MODE (genapic->int_dest_mode) 18#define INT_DEST_MODE (genapic->int_dest_mode)
19#define TARGET_CPUS (genapic->target_cpus()) 19#define TARGET_CPUS (genapic->target_cpus())
20#define vector_allocation_domain (genapic->vector_allocation_domain)
20#define apic_id_registered (genapic->apic_id_registered) 21#define apic_id_registered (genapic->apic_id_registered)
21#define init_apic_ldr (genapic->init_apic_ldr) 22#define init_apic_ldr (genapic->init_apic_ldr)
22#define send_IPI_mask (genapic->send_IPI_mask) 23#define send_IPI_mask (genapic->send_IPI_mask)