diff options
author | Dave Jones <davej@redhat.com> | 2006-12-12 17:41:41 -0500 |
---|---|---|
committer | Dave Jones <davej@redhat.com> | 2006-12-12 17:41:41 -0500 |
commit | c4366889dda8110247be59ca41fddb82951a8c26 (patch) | |
tree | 705c1a996bed8fd48ce94ff33ec9fd00f9b94875 /include/asm-x86_64/msr.h | |
parent | db2fb9db5735cc532fd4fc55e94b9a3c3750378e (diff) | |
parent | e1036502e5263851259d147771226161e5ccc85a (diff) |
Merge ../linus
Conflicts:
drivers/cpufreq/cpufreq.c
Diffstat (limited to 'include/asm-x86_64/msr.h')
-rw-r--r-- | include/asm-x86_64/msr.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h index 207fed998a0b..3227bc93d69b 100644 --- a/include/asm-x86_64/msr.h +++ b/include/asm-x86_64/msr.h | |||
@@ -169,8 +169,8 @@ static inline unsigned int cpuid_edx(unsigned int op) | |||
169 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ | 169 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
170 | #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */ | 170 | #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */ |
171 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ | 171 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
172 | #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */ | 172 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
173 | #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */ | 173 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
174 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */ | 174 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */ |
175 | /* EFER bits: */ | 175 | /* EFER bits: */ |
176 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ | 176 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
@@ -211,6 +211,10 @@ static inline unsigned int cpuid_edx(unsigned int op) | |||
211 | #define MSR_IA32_LASTINTFROMIP 0x1dd | 211 | #define MSR_IA32_LASTINTFROMIP 0x1dd |
212 | #define MSR_IA32_LASTINTTOIP 0x1de | 212 | #define MSR_IA32_LASTINTTOIP 0x1de |
213 | 213 | ||
214 | #define MSR_IA32_PEBS_ENABLE 0x3f1 | ||
215 | #define MSR_IA32_DS_AREA 0x600 | ||
216 | #define MSR_IA32_PERF_CAPABILITIES 0x345 | ||
217 | |||
214 | #define MSR_MTRRfix64K_00000 0x250 | 218 | #define MSR_MTRRfix64K_00000 0x250 |
215 | #define MSR_MTRRfix16K_80000 0x258 | 219 | #define MSR_MTRRfix16K_80000 0x258 |
216 | #define MSR_MTRRfix16K_A0000 0x259 | 220 | #define MSR_MTRRfix16K_A0000 0x259 |
@@ -411,4 +415,13 @@ static inline unsigned int cpuid_edx(unsigned int op) | |||
411 | #define MSR_P4_U2L_ESCR0 0x3b0 | 415 | #define MSR_P4_U2L_ESCR0 0x3b0 |
412 | #define MSR_P4_U2L_ESCR1 0x3b1 | 416 | #define MSR_P4_U2L_ESCR1 0x3b1 |
413 | 417 | ||
418 | /* Intel Core-based CPU performance counters */ | ||
419 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 | ||
420 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | ||
421 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | ||
422 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | ||
423 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | ||
424 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | ||
425 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | ||
426 | |||
414 | #endif | 427 | #endif |