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authorH. Peter Anvin <hpa@zytor.com>2007-05-02 13:27:12 -0400
committerAndi Kleen <andi@basil.nowhere.org>2007-05-02 13:27:12 -0400
commit4bc5aa91fb1e544ad37805520030a0d9fc6e11d3 (patch)
tree207870aad2f53fcec914ea5084de4fdfe1a02a23 /include/asm-x86_64/msr.h
parentb6e3590f8145c77b8fcef3247e2412335221412f (diff)
[PATCH] x86: Clean up x86 control register and MSR macros (corrected)
This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include/asm-x86_64/msr.h')
-rw-r--r--include/asm-x86_64/msr.h274
1 files changed, 5 insertions, 269 deletions
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h
index 902f9a58617e..a524f0325673 100644
--- a/include/asm-x86_64/msr.h
+++ b/include/asm-x86_64/msr.h
@@ -1,6 +1,8 @@
1#ifndef X86_64_MSR_H 1#ifndef X86_64_MSR_H
2#define X86_64_MSR_H 1 2#define X86_64_MSR_H 1
3 3
4#include <asm/msr-index.h>
5
4#ifndef __ASSEMBLY__ 6#ifndef __ASSEMBLY__
5/* 7/*
6 * Access to machine-specific registers (available on 586 and better only) 8 * Access to machine-specific registers (available on 586 and better only)
@@ -157,9 +159,6 @@ static inline unsigned int cpuid_edx(unsigned int op)
157 return edx; 159 return edx;
158} 160}
159 161
160#define MSR_IA32_UCODE_WRITE 0x79
161#define MSR_IA32_UCODE_REV 0x8b
162
163#ifdef CONFIG_SMP 162#ifdef CONFIG_SMP
164void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 163void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
165void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 164void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
@@ -172,269 +171,6 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
172{ 171{
173 wrmsr(msr_no, l, h); 172 wrmsr(msr_no, l, h);
174} 173}
175#endif /* CONFIG_SMP */ 174#endif /* CONFIG_SMP */
176 175#endif /* __ASSEMBLY__ */
177#endif 176#endif /* X86_64_MSR_H */
178
179/* AMD/K8 specific MSRs */
180#define MSR_EFER 0xc0000080 /* extended feature register */
181#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
182#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
183#define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
184#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
185#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
186#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
187#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */
188/* EFER bits: */
189#define _EFER_SCE 0 /* SYSCALL/SYSRET */
190#define _EFER_LME 8 /* Long mode enable */
191#define _EFER_LMA 10 /* Long mode active (read-only) */
192#define _EFER_NX 11 /* No execute enable */
193
194#define EFER_SCE (1<<_EFER_SCE)
195#define EFER_LME (1<<_EFER_LME)
196#define EFER_LMA (1<<_EFER_LMA)
197#define EFER_NX (1<<_EFER_NX)
198
199/* Intel MSRs. Some also available on other CPUs */
200#define MSR_IA32_TSC 0x10
201#define MSR_IA32_PLATFORM_ID 0x17
202
203#define MSR_IA32_PERFCTR0 0xc1
204#define MSR_IA32_PERFCTR1 0xc2
205#define MSR_FSB_FREQ 0xcd
206
207#define MSR_MTRRcap 0x0fe
208#define MSR_IA32_BBL_CR_CTL 0x119
209
210#define MSR_IA32_SYSENTER_CS 0x174
211#define MSR_IA32_SYSENTER_ESP 0x175
212#define MSR_IA32_SYSENTER_EIP 0x176
213
214#define MSR_IA32_MCG_CAP 0x179
215#define MSR_IA32_MCG_STATUS 0x17a
216#define MSR_IA32_MCG_CTL 0x17b
217
218#define MSR_IA32_EVNTSEL0 0x186
219#define MSR_IA32_EVNTSEL1 0x187
220
221#define MSR_IA32_DEBUGCTLMSR 0x1d9
222#define MSR_IA32_LASTBRANCHFROMIP 0x1db
223#define MSR_IA32_LASTBRANCHTOIP 0x1dc
224#define MSR_IA32_LASTINTFROMIP 0x1dd
225#define MSR_IA32_LASTINTTOIP 0x1de
226
227#define MSR_IA32_PEBS_ENABLE 0x3f1
228#define MSR_IA32_DS_AREA 0x600
229#define MSR_IA32_PERF_CAPABILITIES 0x345
230
231#define MSR_MTRRfix64K_00000 0x250
232#define MSR_MTRRfix16K_80000 0x258
233#define MSR_MTRRfix16K_A0000 0x259
234#define MSR_MTRRfix4K_C0000 0x268
235#define MSR_MTRRfix4K_C8000 0x269
236#define MSR_MTRRfix4K_D0000 0x26a
237#define MSR_MTRRfix4K_D8000 0x26b
238#define MSR_MTRRfix4K_E0000 0x26c
239#define MSR_MTRRfix4K_E8000 0x26d
240#define MSR_MTRRfix4K_F0000 0x26e
241#define MSR_MTRRfix4K_F8000 0x26f
242#define MSR_MTRRdefType 0x2ff
243
244#define MSR_IA32_MC0_CTL 0x400
245#define MSR_IA32_MC0_STATUS 0x401
246#define MSR_IA32_MC0_ADDR 0x402
247#define MSR_IA32_MC0_MISC 0x403
248
249#define MSR_P6_PERFCTR0 0xc1
250#define MSR_P6_PERFCTR1 0xc2
251#define MSR_P6_EVNTSEL0 0x186
252#define MSR_P6_EVNTSEL1 0x187
253
254/* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
255#define MSR_K7_EVNTSEL0 0xC0010000
256#define MSR_K7_PERFCTR0 0xC0010004
257#define MSR_K7_EVNTSEL1 0xC0010001
258#define MSR_K7_PERFCTR1 0xC0010005
259#define MSR_K7_EVNTSEL2 0xC0010002
260#define MSR_K7_PERFCTR2 0xC0010006
261#define MSR_K7_EVNTSEL3 0xC0010003
262#define MSR_K7_PERFCTR3 0xC0010007
263#define MSR_K8_TOP_MEM1 0xC001001A
264#define MSR_K8_TOP_MEM2 0xC001001D
265#define MSR_K8_SYSCFG 0xC0010010
266#define MSR_K8_HWCR 0xC0010015
267
268/* K6 MSRs */
269#define MSR_K6_EFER 0xC0000080
270#define MSR_K6_STAR 0xC0000081
271#define MSR_K6_WHCR 0xC0000082
272#define MSR_K6_UWCCR 0xC0000085
273#define MSR_K6_PSOR 0xC0000087
274#define MSR_K6_PFIR 0xC0000088
275
276/* Centaur-Hauls/IDT defined MSRs. */
277#define MSR_IDT_FCR1 0x107
278#define MSR_IDT_FCR2 0x108
279#define MSR_IDT_FCR3 0x109
280#define MSR_IDT_FCR4 0x10a
281
282#define MSR_IDT_MCR0 0x110
283#define MSR_IDT_MCR1 0x111
284#define MSR_IDT_MCR2 0x112
285#define MSR_IDT_MCR3 0x113
286#define MSR_IDT_MCR4 0x114
287#define MSR_IDT_MCR5 0x115
288#define MSR_IDT_MCR6 0x116
289#define MSR_IDT_MCR7 0x117
290#define MSR_IDT_MCR_CTRL 0x120
291
292/* VIA Cyrix defined MSRs*/
293#define MSR_VIA_FCR 0x1107
294#define MSR_VIA_LONGHAUL 0x110a
295#define MSR_VIA_RNG 0x110b
296#define MSR_VIA_BCR2 0x1147
297
298/* Intel defined MSRs. */
299#define MSR_IA32_P5_MC_ADDR 0
300#define MSR_IA32_P5_MC_TYPE 1
301#define MSR_IA32_PLATFORM_ID 0x17
302#define MSR_IA32_EBL_CR_POWERON 0x2a
303
304#define MSR_IA32_APICBASE 0x1b
305#define MSR_IA32_APICBASE_BSP (1<<8)
306#define MSR_IA32_APICBASE_ENABLE (1<<11)
307#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
308
309/* P4/Xeon+ specific */
310#define MSR_IA32_MCG_EAX 0x180
311#define MSR_IA32_MCG_EBX 0x181
312#define MSR_IA32_MCG_ECX 0x182
313#define MSR_IA32_MCG_EDX 0x183
314#define MSR_IA32_MCG_ESI 0x184
315#define MSR_IA32_MCG_EDI 0x185
316#define MSR_IA32_MCG_EBP 0x186
317#define MSR_IA32_MCG_ESP 0x187
318#define MSR_IA32_MCG_EFLAGS 0x188
319#define MSR_IA32_MCG_EIP 0x189
320#define MSR_IA32_MCG_RESERVED 0x18A
321
322#define MSR_P6_EVNTSEL0 0x186
323#define MSR_P6_EVNTSEL1 0x187
324
325#define MSR_IA32_PERF_STATUS 0x198
326#define MSR_IA32_PERF_CTL 0x199
327
328#define MSR_IA32_MPERF 0xE7
329#define MSR_IA32_APERF 0xE8
330
331#define MSR_IA32_THERM_CONTROL 0x19a
332#define MSR_IA32_THERM_INTERRUPT 0x19b
333#define MSR_IA32_THERM_STATUS 0x19c
334#define MSR_IA32_MISC_ENABLE 0x1a0
335
336#define MSR_IA32_DEBUGCTLMSR 0x1d9
337#define MSR_IA32_LASTBRANCHFROMIP 0x1db
338#define MSR_IA32_LASTBRANCHTOIP 0x1dc
339#define MSR_IA32_LASTINTFROMIP 0x1dd
340#define MSR_IA32_LASTINTTOIP 0x1de
341
342#define MSR_IA32_MC0_CTL 0x400
343#define MSR_IA32_MC0_STATUS 0x401
344#define MSR_IA32_MC0_ADDR 0x402
345#define MSR_IA32_MC0_MISC 0x403
346
347/* Pentium IV performance counter MSRs */
348#define MSR_P4_BPU_PERFCTR0 0x300
349#define MSR_P4_BPU_PERFCTR1 0x301
350#define MSR_P4_BPU_PERFCTR2 0x302
351#define MSR_P4_BPU_PERFCTR3 0x303
352#define MSR_P4_MS_PERFCTR0 0x304
353#define MSR_P4_MS_PERFCTR1 0x305
354#define MSR_P4_MS_PERFCTR2 0x306
355#define MSR_P4_MS_PERFCTR3 0x307
356#define MSR_P4_FLAME_PERFCTR0 0x308
357#define MSR_P4_FLAME_PERFCTR1 0x309
358#define MSR_P4_FLAME_PERFCTR2 0x30a
359#define MSR_P4_FLAME_PERFCTR3 0x30b
360#define MSR_P4_IQ_PERFCTR0 0x30c
361#define MSR_P4_IQ_PERFCTR1 0x30d
362#define MSR_P4_IQ_PERFCTR2 0x30e
363#define MSR_P4_IQ_PERFCTR3 0x30f
364#define MSR_P4_IQ_PERFCTR4 0x310
365#define MSR_P4_IQ_PERFCTR5 0x311
366#define MSR_P4_BPU_CCCR0 0x360
367#define MSR_P4_BPU_CCCR1 0x361
368#define MSR_P4_BPU_CCCR2 0x362
369#define MSR_P4_BPU_CCCR3 0x363
370#define MSR_P4_MS_CCCR0 0x364
371#define MSR_P4_MS_CCCR1 0x365
372#define MSR_P4_MS_CCCR2 0x366
373#define MSR_P4_MS_CCCR3 0x367
374#define MSR_P4_FLAME_CCCR0 0x368
375#define MSR_P4_FLAME_CCCR1 0x369
376#define MSR_P4_FLAME_CCCR2 0x36a
377#define MSR_P4_FLAME_CCCR3 0x36b
378#define MSR_P4_IQ_CCCR0 0x36c
379#define MSR_P4_IQ_CCCR1 0x36d
380#define MSR_P4_IQ_CCCR2 0x36e
381#define MSR_P4_IQ_CCCR3 0x36f
382#define MSR_P4_IQ_CCCR4 0x370
383#define MSR_P4_IQ_CCCR5 0x371
384#define MSR_P4_ALF_ESCR0 0x3ca
385#define MSR_P4_ALF_ESCR1 0x3cb
386#define MSR_P4_BPU_ESCR0 0x3b2
387#define MSR_P4_BPU_ESCR1 0x3b3
388#define MSR_P4_BSU_ESCR0 0x3a0
389#define MSR_P4_BSU_ESCR1 0x3a1
390#define MSR_P4_CRU_ESCR0 0x3b8
391#define MSR_P4_CRU_ESCR1 0x3b9
392#define MSR_P4_CRU_ESCR2 0x3cc
393#define MSR_P4_CRU_ESCR3 0x3cd
394#define MSR_P4_CRU_ESCR4 0x3e0
395#define MSR_P4_CRU_ESCR5 0x3e1
396#define MSR_P4_DAC_ESCR0 0x3a8
397#define MSR_P4_DAC_ESCR1 0x3a9
398#define MSR_P4_FIRM_ESCR0 0x3a4
399#define MSR_P4_FIRM_ESCR1 0x3a5
400#define MSR_P4_FLAME_ESCR0 0x3a6
401#define MSR_P4_FLAME_ESCR1 0x3a7
402#define MSR_P4_FSB_ESCR0 0x3a2
403#define MSR_P4_FSB_ESCR1 0x3a3
404#define MSR_P4_IQ_ESCR0 0x3ba
405#define MSR_P4_IQ_ESCR1 0x3bb
406#define MSR_P4_IS_ESCR0 0x3b4
407#define MSR_P4_IS_ESCR1 0x3b5
408#define MSR_P4_ITLB_ESCR0 0x3b6
409#define MSR_P4_ITLB_ESCR1 0x3b7
410#define MSR_P4_IX_ESCR0 0x3c8
411#define MSR_P4_IX_ESCR1 0x3c9
412#define MSR_P4_MOB_ESCR0 0x3aa
413#define MSR_P4_MOB_ESCR1 0x3ab
414#define MSR_P4_MS_ESCR0 0x3c0
415#define MSR_P4_MS_ESCR1 0x3c1
416#define MSR_P4_PMH_ESCR0 0x3ac
417#define MSR_P4_PMH_ESCR1 0x3ad
418#define MSR_P4_RAT_ESCR0 0x3bc
419#define MSR_P4_RAT_ESCR1 0x3bd
420#define MSR_P4_SAAT_ESCR0 0x3ae
421#define MSR_P4_SAAT_ESCR1 0x3af
422#define MSR_P4_SSU_ESCR0 0x3be
423#define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
424#define MSR_P4_TBPU_ESCR0 0x3c2
425#define MSR_P4_TBPU_ESCR1 0x3c3
426#define MSR_P4_TC_ESCR0 0x3c4
427#define MSR_P4_TC_ESCR1 0x3c5
428#define MSR_P4_U2L_ESCR0 0x3b0
429#define MSR_P4_U2L_ESCR1 0x3b1
430
431/* Intel Core-based CPU performance counters */
432#define MSR_CORE_PERF_FIXED_CTR0 0x309
433#define MSR_CORE_PERF_FIXED_CTR1 0x30a
434#define MSR_CORE_PERF_FIXED_CTR2 0x30b
435#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
436#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
437#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
438#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
439
440#endif
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