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authorJeff Garzik <jeff@garzik.org>2006-03-29 17:18:49 -0500
committerJeff Garzik <jeff@garzik.org>2006-03-29 17:18:49 -0500
commite02a4cabfcb9a999b74a2e2e6f13ffcb7ff2d606 (patch)
tree2f3db60be4c57eca2a4c3ab3f3122dcf1ec0c624 /include/asm-x86_64/io.h
parent600511e86babe3727264a0883a3a264f6fb6caf5 (diff)
parentf3cab8a0b1a772dc8b055b7affa567a366627c9e (diff)
Merge branch 'master'
Diffstat (limited to 'include/asm-x86_64/io.h')
-rw-r--r--include/asm-x86_64/io.h26
1 files changed, 3 insertions, 23 deletions
diff --git a/include/asm-x86_64/io.h b/include/asm-x86_64/io.h
index a85fe8370820..cafdfb37f0d8 100644
--- a/include/asm-x86_64/io.h
+++ b/include/asm-x86_64/io.h
@@ -135,6 +135,9 @@ static inline void __iomem * ioremap (unsigned long offset, unsigned long size)
135 return __ioremap(offset, size, 0); 135 return __ioremap(offset, size, 0);
136} 136}
137 137
138extern void *early_ioremap(unsigned long addr, unsigned long size);
139extern void early_iounmap(void *addr, unsigned long size);
140
138/* 141/*
139 * This one maps high address device memory and turns off caching for that area. 142 * This one maps high address device memory and turns off caching for that area.
140 * it's useful if some control registers are in such an area and write combining 143 * it's useful if some control registers are in such an area and write combining
@@ -143,11 +146,6 @@ static inline void __iomem * ioremap (unsigned long offset, unsigned long size)
143extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size); 146extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
144extern void iounmap(volatile void __iomem *addr); 147extern void iounmap(volatile void __iomem *addr);
145 148
146/* Use normal IO mappings for DMI */
147#define dmi_ioremap ioremap
148#define dmi_iounmap(x,l) iounmap(x)
149#define dmi_alloc(l) kmalloc(l, GFP_ATOMIC)
150
151/* 149/*
152 * ISA I/O bus memory addresses are 1:1 with the physical address. 150 * ISA I/O bus memory addresses are 1:1 with the physical address.
153 */ 151 */
@@ -202,23 +200,6 @@ static inline __u64 __readq(const volatile void __iomem *addr)
202 200
203#define mmiowb() 201#define mmiowb()
204 202
205#ifdef CONFIG_UNORDERED_IO
206static inline void __writel(__u32 val, volatile void __iomem *addr)
207{
208 volatile __u32 __iomem *target = addr;
209 asm volatile("movnti %1,%0"
210 : "=m" (*target)
211 : "r" (val) : "memory");
212}
213
214static inline void __writeq(__u64 val, volatile void __iomem *addr)
215{
216 volatile __u64 __iomem *target = addr;
217 asm volatile("movnti %1,%0"
218 : "=m" (*target)
219 : "r" (val) : "memory");
220}
221#else
222static inline void __writel(__u32 b, volatile void __iomem *addr) 203static inline void __writel(__u32 b, volatile void __iomem *addr)
223{ 204{
224 *(__force volatile __u32 *)addr = b; 205 *(__force volatile __u32 *)addr = b;
@@ -227,7 +208,6 @@ static inline void __writeq(__u64 b, volatile void __iomem *addr)
227{ 208{
228 *(__force volatile __u64 *)addr = b; 209 *(__force volatile __u64 *)addr = b;
229} 210}
230#endif
231static inline void __writeb(__u8 b, volatile void __iomem *addr) 211static inline void __writeb(__u8 b, volatile void __iomem *addr)
232{ 212{
233 *(__force volatile __u8 *)addr = b; 213 *(__force volatile __u8 *)addr = b;