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authorAndi Kleen <ak@suse.de>2005-09-12 12:49:24 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-12 13:49:58 -0400
commite5bc8b6baf86538f3d0407cf0880f86aec828a13 (patch)
treeb67a98a866a51286fd342d08b27b511826875138 /include/asm-x86_64/hw_irq.h
parent83b942bd3437d84d6ddf582477120b6b86369052 (diff)
[PATCH] x86-64: Make remote TLB flush more scalable
Instead of using a global spinlock to protect the state of the remote TLB flush use a lock and state for each sending CPU. To tell the receiver where to look for the state use 8 different call vectors. Each CPU uses a specific vector to trigger flushes on other CPUs. Depending on the received vector the target CPUs look into the right per cpu variable for the flush data. When the system has more than 8 CPUs they are hashed to the 8 available vectors. The limited global vector space forces us to this right now. In future when interrupts are split into per CPU domains this could be fixed, at the cost of needing more IPIs in flat mode. Also some minor cleanup in the smp flush code and remove some outdated debug code. Requires patch to move cpu_possible_map setup earlier. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64/hw_irq.h')
-rw-r--r--include/asm-x86_64/hw_irq.h17
1 files changed, 9 insertions, 8 deletions
diff --git a/include/asm-x86_64/hw_irq.h b/include/asm-x86_64/hw_irq.h
index 2b5cb2865d21..d9212eb4e894 100644
--- a/include/asm-x86_64/hw_irq.h
+++ b/include/asm-x86_64/hw_irq.h
@@ -50,14 +50,15 @@ struct hw_interrupt_type;
50 */ 50 */
51#define SPURIOUS_APIC_VECTOR 0xff 51#define SPURIOUS_APIC_VECTOR 0xff
52#define ERROR_APIC_VECTOR 0xfe 52#define ERROR_APIC_VECTOR 0xfe
53#define INVALIDATE_TLB_VECTOR 0xfd 53#define RESCHEDULE_VECTOR 0xfd
54#define RESCHEDULE_VECTOR 0xfc 54#define CALL_FUNCTION_VECTOR 0xfc
55#define TASK_MIGRATION_VECTOR 0xfb 55#define KDB_VECTOR 0xfb /* reserved for KDB */
56#define CALL_FUNCTION_VECTOR 0xfa 56#define THERMAL_APIC_VECTOR 0xfa
57#define KDB_VECTOR 0xf9 57/* 0xf9 free */
58 58#define INVALIDATE_TLB_VECTOR_END 0xf8
59#define THERMAL_APIC_VECTOR 0xf0 59#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f8 used for TLB flush */
60 60
61#define NUM_INVALIDATE_TLB_VECTORS 8
61 62
62/* 63/*
63 * Local APIC timer IRQ vector is on a different priority level, 64 * Local APIC timer IRQ vector is on a different priority level,