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authorVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>2006-01-11 16:44:24 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-11 22:04:54 -0500
commitd25bf7e5fe73b5b6d2246ab0be08ae35d718456b (patch)
tree472749fef9b017e9a4d94f9e07a29dc44c3294cb /include/asm-x86_64/apic.h
parent6eb0a0fd059598ee0d49c6283ce25cccd743e9fc (diff)
[PATCH] x86_64: Handle missing local APIC timer interrupts on C3 state
Whenever we see that a CPU is capable of C3 (during ACPI cstate init), we disable local APIC timer and switch to using a broadcast from external timer interrupt (IRQ 0). Patch below adds the code for x86_64. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64/apic.h')
-rw-r--r--include/asm-x86_64/apic.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/asm-x86_64/apic.h b/include/asm-x86_64/apic.h
index 5647b7de1749..1768ce719156 100644
--- a/include/asm-x86_64/apic.h
+++ b/include/asm-x86_64/apic.h
@@ -113,6 +113,12 @@ extern int disable_timer_pin_1;
113 113
114extern void setup_threshold_lvt(unsigned long lvt_off); 114extern void setup_threshold_lvt(unsigned long lvt_off);
115 115
116void smp_send_timer_broadcast_ipi(void);
117void switch_APIC_timer_to_ipi(void *cpumask);
118void switch_ipi_to_APIC_timer(void *cpumask);
119
120#define ARCH_APICTIMER_STOPS_ON_C3 1
121
116#endif /* CONFIG_X86_LOCAL_APIC */ 122#endif /* CONFIG_X86_LOCAL_APIC */
117 123
118extern unsigned boot_cpu_id; 124extern unsigned boot_cpu_id;