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authorJacob Shin <jacob.shin@amd.com>2005-11-05 11:25:53 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-14 22:55:13 -0500
commit89b831ef8bf5cfbb357dbc0a2e07700d7f20eec5 (patch)
tree25118081599eab69bd20d1a1b34ba0f8f679f24f /include/asm-x86_64/apic.h
parent979edfadbae2286eec5b46143c00e81bca96498e (diff)
[PATCH] x86_64: Support for AMD specific MCE Threshold.
MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F. This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations. The user may interface through sysfs files in order to change the threshold configuration. bank%d/error_count - reads current error count, write to clear. bank%d/interrupt_enable - set/clear interrupt enable. bank%d/threshold_limit - read/write the threshold limit. APIC vector 0xF9 in hw_irq.h. 5 software defined bank ids in mce.h. new apic.c function to setup threshold apic lvt. defaults to interrupt off, count enabled, and threshold limit max. sysfs interface created on /sys/devices/system/threshold. AK: added some ifdefs to make it compile on UP Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64/apic.h')
-rw-r--r--include/asm-x86_64/apic.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-x86_64/apic.h b/include/asm-x86_64/apic.h
index 6c5d5ca8383a..5647b7de1749 100644
--- a/include/asm-x86_64/apic.h
+++ b/include/asm-x86_64/apic.h
@@ -111,6 +111,8 @@ extern unsigned int nmi_watchdog;
111 111
112extern int disable_timer_pin_1; 112extern int disable_timer_pin_1;
113 113
114extern void setup_threshold_lvt(unsigned long lvt_off);
115
114#endif /* CONFIG_X86_LOCAL_APIC */ 116#endif /* CONFIG_X86_LOCAL_APIC */
115 117
116extern unsigned boot_cpu_id; 118extern unsigned boot_cpu_id;