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authorIngo Molnar <mingo@elte.hu>2008-09-19 03:15:50 -0400
committerIngo Molnar <mingo@elte.hu>2008-09-19 03:15:50 -0400
commit5e51900be6c15488b80343d3c3e62d4d605ba9a9 (patch)
tree99e60bbc949e066503b598893998286c8a42861d /include/asm-x86
parent998564789137921acae9e367b61c5a1dc295653d (diff)
parentadee14b2e1557d0a8559f29681732d05a89dfc35 (diff)
Merge commit 'v2.6.27-rc6' into x86/cleanups
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/cpufeature.h11
-rw-r--r--include/asm-x86/kvm_host.h2
-rw-r--r--include/asm-x86/required-features.h8
3 files changed, 14 insertions, 7 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 762f6a6bc707..9489283a4bcf 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -72,14 +72,15 @@
72#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ 72#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
73#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ 73#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
74#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 74#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
75#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 75#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
76#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 76#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
77#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ 77#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
78#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ 78#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
79#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ 79#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
80#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ 80#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
81#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ 81#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
82#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ 82#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */
83#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
83 84
84/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 85/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
85#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ 86#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 0f3c53114614..c2e34c275900 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -722,7 +722,7 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
722 722
723#define __kvm_handle_fault_on_reboot(insn) \ 723#define __kvm_handle_fault_on_reboot(insn) \
724 "666: " insn "\n\t" \ 724 "666: " insn "\n\t" \
725 ".pushsection .text.fixup, \"ax\" \n" \ 725 ".pushsection .fixup, \"ax\" \n" \
726 "667: \n\t" \ 726 "667: \n\t" \
727 KVM_EX_PUSH " $666b \n\t" \ 727 KVM_EX_PUSH " $666b \n\t" \
728 "jmp kvm_handle_fault_on_reboot \n\t" \ 728 "jmp kvm_handle_fault_on_reboot \n\t" \
diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h
index adec887dd7cd..5c2ff4bc2980 100644
--- a/include/asm-x86/required-features.h
+++ b/include/asm-x86/required-features.h
@@ -41,6 +41,12 @@
41# define NEED_3DNOW 0 41# define NEED_3DNOW 0
42#endif 42#endif
43 43
44#if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64)
45# define NEED_NOPL (1<<(X86_FEATURE_NOPL & 31))
46#else
47# define NEED_NOPL 0
48#endif
49
44#ifdef CONFIG_X86_64 50#ifdef CONFIG_X86_64
45#define NEED_PSE 0 51#define NEED_PSE 0
46#define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) 52#define NEED_MSR (1<<(X86_FEATURE_MSR & 31))
@@ -67,7 +73,7 @@
67#define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW) 73#define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW)
68 74
69#define REQUIRED_MASK2 0 75#define REQUIRED_MASK2 0
70#define REQUIRED_MASK3 0 76#define REQUIRED_MASK3 (NEED_NOPL)
71#define REQUIRED_MASK4 0 77#define REQUIRED_MASK4 0
72#define REQUIRED_MASK5 0 78#define REQUIRED_MASK5 0
73#define REQUIRED_MASK6 0 79#define REQUIRED_MASK6 0