diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-05-27 12:47:13 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-06-02 06:29:31 -0400 |
commit | c1f64a58003fd2efaa725a857e269a15f765791a (patch) | |
tree | 68a09bddb1c16fbcc748df41ddca4edb4442cb56 /include/asm-x86 | |
parent | 1beee8dc8cf58e3f605bd7b34d7a39939be7d8d2 (diff) |
x86: MMIO and gcc re-ordering issue
On Tue, 27 May 2008, Linus Torvalds wrote:
>
> Expecting people to fix up all drivers is simply not going to happen. And
> serializing things shouldn't be *that* expensive. People who cannot take
> the expense can continue to use the magic __raw_writel() etc stuff.
Of course, for non-x86, you kind of have to expect drivers to be
well-behaved, so non-x86 can probably avoid this simply because there are
less relevant drivers involved.
Here's a UNTESTED patch for x86 that may or may not compile and work, and
which serializes (on a compiler level) the IO accesses against regular
memory accesses.
__read[bwlq]()/__write[bwlq]() are not serialized with a :"memory"
barrier, although since they still use "asm volatile" I suspect that i
practice they are probably serial too. Did not look very closely at any
generated code (only did a trivial test to see that the code looks
*roughly* correct).
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86')
-rw-r--r-- | include/asm-x86/io.h | 56 | ||||
-rw-r--r-- | include/asm-x86/io_32.h | 49 | ||||
-rw-r--r-- | include/asm-x86/io_64.h | 71 |
3 files changed, 56 insertions, 120 deletions
diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h index d5b11f60dbd0..8e9eca93f9b9 100644 --- a/include/asm-x86/io.h +++ b/include/asm-x86/io.h | |||
@@ -3,6 +3,62 @@ | |||
3 | 3 | ||
4 | #define ARCH_HAS_IOREMAP_WC | 4 | #define ARCH_HAS_IOREMAP_WC |
5 | 5 | ||
6 | #include <linux/compiler.h> | ||
7 | |||
8 | #define build_mmio_read(name, size, type, reg, barrier) \ | ||
9 | static inline type name(const volatile void __iomem *addr) \ | ||
10 | { type ret; asm volatile("mov" size " %1,%0":"=" reg (ret) \ | ||
11 | :"m" (*(volatile type __force *)addr) barrier); return ret; } | ||
12 | |||
13 | #define build_mmio_write(name, size, type, reg, barrier) \ | ||
14 | static inline void name(type val, volatile void __iomem *addr) \ | ||
15 | { asm volatile("mov" size " %0,%1": :reg (val), \ | ||
16 | "m" (*(volatile type __force *)addr) barrier); } | ||
17 | |||
18 | build_mmio_read(readb, "b", unsigned char, "q", :"memory") | ||
19 | build_mmio_read(readw, "w", unsigned short, "r", :"memory") | ||
20 | build_mmio_read(readl, "l", unsigned int, "r", :"memory") | ||
21 | |||
22 | build_mmio_read(__readb, "b", unsigned char, "q", ) | ||
23 | build_mmio_read(__readw, "w", unsigned short, "r", ) | ||
24 | build_mmio_read(__readl, "l", unsigned int, "r", ) | ||
25 | |||
26 | build_mmio_write(writeb, "b", unsigned char, "q", :"memory") | ||
27 | build_mmio_write(writew, "w", unsigned short, "r", :"memory") | ||
28 | build_mmio_write(writel, "l", unsigned int, "r", :"memory") | ||
29 | |||
30 | build_mmio_write(__writeb, "b", unsigned char, "q", ) | ||
31 | build_mmio_write(__writew, "w", unsigned short, "r", ) | ||
32 | build_mmio_write(__writel, "l", unsigned int, "r", ) | ||
33 | |||
34 | #define readb_relaxed(a) __readb(a) | ||
35 | #define readw_relaxed(a) __readw(a) | ||
36 | #define readl_relaxed(a) __readl(a) | ||
37 | #define __raw_readb __readb | ||
38 | #define __raw_readw __readw | ||
39 | #define __raw_readl __readl | ||
40 | |||
41 | #define __raw_writeb __writeb | ||
42 | #define __raw_writew __writew | ||
43 | #define __raw_writel __writel | ||
44 | |||
45 | #define mmiowb() barrier() | ||
46 | |||
47 | #ifdef CONFIG_X86_64 | ||
48 | build_mmio_read(readq, "q", unsigned long, "r", :"memory") | ||
49 | build_mmio_read(__readq, "q", unsigned long, "r", ) | ||
50 | build_mmio_write(writeq, "q", unsigned long, "r", :"memory") | ||
51 | build_mmio_write(__writeq, "q", unsigned long, "r", ) | ||
52 | |||
53 | #define readq_relaxed(a) __readq(a) | ||
54 | #define __raw_readq __readq | ||
55 | #define __raw_writeq writeq | ||
56 | |||
57 | /* Let people know we have them */ | ||
58 | #define readq readq | ||
59 | #define writeq writeq | ||
60 | #endif | ||
61 | |||
6 | #ifdef CONFIG_X86_32 | 62 | #ifdef CONFIG_X86_32 |
7 | # include "io_32.h" | 63 | # include "io_32.h" |
8 | #else | 64 | #else |
diff --git a/include/asm-x86/io_32.h b/include/asm-x86/io_32.h index 049e81e797a0..d71be8df9797 100644 --- a/include/asm-x86/io_32.h +++ b/include/asm-x86/io_32.h | |||
@@ -149,55 +149,6 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); | |||
149 | #define virt_to_bus virt_to_phys | 149 | #define virt_to_bus virt_to_phys |
150 | #define bus_to_virt phys_to_virt | 150 | #define bus_to_virt phys_to_virt |
151 | 151 | ||
152 | /* | ||
153 | * readX/writeX() are used to access memory mapped devices. On some | ||
154 | * architectures the memory mapped IO stuff needs to be accessed | ||
155 | * differently. On the x86 architecture, we just read/write the | ||
156 | * memory location directly. | ||
157 | */ | ||
158 | |||
159 | static inline unsigned char readb(const volatile void __iomem *addr) | ||
160 | { | ||
161 | return *(volatile unsigned char __force *)addr; | ||
162 | } | ||
163 | |||
164 | static inline unsigned short readw(const volatile void __iomem *addr) | ||
165 | { | ||
166 | return *(volatile unsigned short __force *)addr; | ||
167 | } | ||
168 | |||
169 | static inline unsigned int readl(const volatile void __iomem *addr) | ||
170 | { | ||
171 | return *(volatile unsigned int __force *) addr; | ||
172 | } | ||
173 | |||
174 | #define readb_relaxed(addr) readb(addr) | ||
175 | #define readw_relaxed(addr) readw(addr) | ||
176 | #define readl_relaxed(addr) readl(addr) | ||
177 | #define __raw_readb readb | ||
178 | #define __raw_readw readw | ||
179 | #define __raw_readl readl | ||
180 | |||
181 | static inline void writeb(unsigned char b, volatile void __iomem *addr) | ||
182 | { | ||
183 | *(volatile unsigned char __force *)addr = b; | ||
184 | } | ||
185 | |||
186 | static inline void writew(unsigned short b, volatile void __iomem *addr) | ||
187 | { | ||
188 | *(volatile unsigned short __force *)addr = b; | ||
189 | } | ||
190 | |||
191 | static inline void writel(unsigned int b, volatile void __iomem *addr) | ||
192 | { | ||
193 | *(volatile unsigned int __force *)addr = b; | ||
194 | } | ||
195 | #define __raw_writeb writeb | ||
196 | #define __raw_writew writew | ||
197 | #define __raw_writel writel | ||
198 | |||
199 | #define mmiowb() | ||
200 | |||
201 | static inline void | 152 | static inline void |
202 | memset_io(volatile void __iomem *addr, unsigned char val, int count) | 153 | memset_io(volatile void __iomem *addr, unsigned char val, int count) |
203 | { | 154 | { |
diff --git a/include/asm-x86/io_64.h b/include/asm-x86/io_64.h index 0930bedf9e4d..ddd8058a5026 100644 --- a/include/asm-x86/io_64.h +++ b/include/asm-x86/io_64.h | |||
@@ -204,77 +204,6 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); | |||
204 | #define virt_to_bus virt_to_phys | 204 | #define virt_to_bus virt_to_phys |
205 | #define bus_to_virt phys_to_virt | 205 | #define bus_to_virt phys_to_virt |
206 | 206 | ||
207 | /* | ||
208 | * readX/writeX() are used to access memory mapped devices. On some | ||
209 | * architectures the memory mapped IO stuff needs to be accessed | ||
210 | * differently. On the x86 architecture, we just read/write the | ||
211 | * memory location directly. | ||
212 | */ | ||
213 | |||
214 | static inline __u8 __readb(const volatile void __iomem *addr) | ||
215 | { | ||
216 | return *(__force volatile __u8 *)addr; | ||
217 | } | ||
218 | |||
219 | static inline __u16 __readw(const volatile void __iomem *addr) | ||
220 | { | ||
221 | return *(__force volatile __u16 *)addr; | ||
222 | } | ||
223 | |||
224 | static __always_inline __u32 __readl(const volatile void __iomem *addr) | ||
225 | { | ||
226 | return *(__force volatile __u32 *)addr; | ||
227 | } | ||
228 | |||
229 | static inline __u64 __readq(const volatile void __iomem *addr) | ||
230 | { | ||
231 | return *(__force volatile __u64 *)addr; | ||
232 | } | ||
233 | |||
234 | #define readb(x) __readb(x) | ||
235 | #define readw(x) __readw(x) | ||
236 | #define readl(x) __readl(x) | ||
237 | #define readq(x) __readq(x) | ||
238 | #define readb_relaxed(a) readb(a) | ||
239 | #define readw_relaxed(a) readw(a) | ||
240 | #define readl_relaxed(a) readl(a) | ||
241 | #define readq_relaxed(a) readq(a) | ||
242 | #define __raw_readb readb | ||
243 | #define __raw_readw readw | ||
244 | #define __raw_readl readl | ||
245 | #define __raw_readq readq | ||
246 | |||
247 | #define mmiowb() | ||
248 | |||
249 | static inline void __writel(__u32 b, volatile void __iomem *addr) | ||
250 | { | ||
251 | *(__force volatile __u32 *)addr = b; | ||
252 | } | ||
253 | |||
254 | static inline void __writeq(__u64 b, volatile void __iomem *addr) | ||
255 | { | ||
256 | *(__force volatile __u64 *)addr = b; | ||
257 | } | ||
258 | |||
259 | static inline void __writeb(__u8 b, volatile void __iomem *addr) | ||
260 | { | ||
261 | *(__force volatile __u8 *)addr = b; | ||
262 | } | ||
263 | |||
264 | static inline void __writew(__u16 b, volatile void __iomem *addr) | ||
265 | { | ||
266 | *(__force volatile __u16 *)addr = b; | ||
267 | } | ||
268 | |||
269 | #define writeq(val, addr) __writeq((val), (addr)) | ||
270 | #define writel(val, addr) __writel((val), (addr)) | ||
271 | #define writew(val, addr) __writew((val), (addr)) | ||
272 | #define writeb(val, addr) __writeb((val), (addr)) | ||
273 | #define __raw_writeb writeb | ||
274 | #define __raw_writew writew | ||
275 | #define __raw_writel writel | ||
276 | #define __raw_writeq writeq | ||
277 | |||
278 | void __memcpy_fromio(void *, unsigned long, unsigned); | 207 | void __memcpy_fromio(void *, unsigned long, unsigned); |
279 | void __memcpy_toio(unsigned long, const void *, unsigned); | 208 | void __memcpy_toio(unsigned long, const void *, unsigned); |
280 | 209 | ||