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authorThomas Gleixner <tglx@linutronix.de>2008-01-30 07:30:14 -0500
committerIngo Molnar <mingo@elte.hu>2008-01-30 07:30:14 -0500
commit2d539553c96771bc8f77156f27500d35e1fe114c (patch)
tree7b0b75e25e2ceb052849e14a442c503f20551381 /include/asm-x86
parent77e463d1040d6310211ac5162729f5d4afc4dd8c (diff)
x86: unify include/asm-x86/apicdef_32/64.h
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/apicdef.h399
-rw-r--r--include/asm-x86/apicdef_32.h375
-rw-r--r--include/asm-x86/apicdef_64.h392
3 files changed, 397 insertions, 769 deletions
diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h
index 4542c220bf4d..83ac1e6e3625 100644
--- a/include/asm-x86/apicdef.h
+++ b/include/asm-x86/apicdef.h
@@ -1,5 +1,400 @@
1#ifndef _ASM_X86_APICDEF_H
2#define _ASM_X86_APICDEF_H
3
4/*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
10
11#define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13#define APIC_ID 0x20
14
15#ifdef CONFIG_X86_64
16# define APIC_ID_MASK (0xFFu<<24)
17# define GET_APIC_ID(x) (((x)>>24)&0xFFu)
18# define SET_APIC_ID(x) (((x)<<24))
19#endif
20
21#define APIC_LVR 0x30
22#define APIC_LVR_MASK 0xFF00FF
23#define GET_APIC_VERSION(x) ((x)&0xFFu)
24#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu)
25#define APIC_INTEGRATED(x) ((x)&0xF0u)
26#define APIC_XAPIC(x) ((x) >= 0x14)
27#define APIC_TASKPRI 0x80
28#define APIC_TPRI_MASK 0xFFu
29#define APIC_ARBPRI 0x90
30#define APIC_ARBPRI_MASK 0xFFu
31#define APIC_PROCPRI 0xA0
32#define APIC_EOI 0xB0
33#define APIC_EIO_ACK 0x0
34#define APIC_RRR 0xC0
35#define APIC_LDR 0xD0
36#define APIC_LDR_MASK (0xFFu<<24)
37#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu)
38#define SET_APIC_LOGICAL_ID(x) (((x)<<24))
39#define APIC_ALL_CPUS 0xFFu
40#define APIC_DFR 0xE0
41#define APIC_DFR_CLUSTER 0x0FFFFFFFul
42#define APIC_DFR_FLAT 0xFFFFFFFFul
43#define APIC_SPIV 0xF0
44#define APIC_SPIV_FOCUS_DISABLED (1<<9)
45#define APIC_SPIV_APIC_ENABLED (1<<8)
46#define APIC_ISR 0x100
47#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
48#define APIC_TMR 0x180
49#define APIC_IRR 0x200
50#define APIC_ESR 0x280
51#define APIC_ESR_SEND_CS 0x00001
52#define APIC_ESR_RECV_CS 0x00002
53#define APIC_ESR_SEND_ACC 0x00004
54#define APIC_ESR_RECV_ACC 0x00008
55#define APIC_ESR_SENDILL 0x00020
56#define APIC_ESR_RECVILL 0x00040
57#define APIC_ESR_ILLREGA 0x00080
58#define APIC_ICR 0x300
59#define APIC_DEST_SELF 0x40000
60#define APIC_DEST_ALLINC 0x80000
61#define APIC_DEST_ALLBUT 0xC0000
62#define APIC_ICR_RR_MASK 0x30000
63#define APIC_ICR_RR_INVALID 0x00000
64#define APIC_ICR_RR_INPROG 0x10000
65#define APIC_ICR_RR_VALID 0x20000
66#define APIC_INT_LEVELTRIG 0x08000
67#define APIC_INT_ASSERT 0x04000
68#define APIC_ICR_BUSY 0x01000
69#define APIC_DEST_LOGICAL 0x00800
70#define APIC_DEST_PHYSICAL 0x00000
71#define APIC_DM_FIXED 0x00000
72#define APIC_DM_LOWEST 0x00100
73#define APIC_DM_SMI 0x00200
74#define APIC_DM_REMRD 0x00300
75#define APIC_DM_NMI 0x00400
76#define APIC_DM_INIT 0x00500
77#define APIC_DM_STARTUP 0x00600
78#define APIC_DM_EXTINT 0x00700
79#define APIC_VECTOR_MASK 0x000FF
80#define APIC_ICR2 0x310
81#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
82#define SET_APIC_DEST_FIELD(x) ((x)<<24)
83#define APIC_LVTT 0x320
84#define APIC_LVTTHMR 0x330
85#define APIC_LVTPC 0x340
86#define APIC_LVT0 0x350
87#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
88#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
89#define SET_APIC_TIMER_BASE(x) (((x)<<18))
90#define APIC_TIMER_BASE_CLKIN 0x0
91#define APIC_TIMER_BASE_TMBASE 0x1
92#define APIC_TIMER_BASE_DIV 0x2
93#define APIC_LVT_TIMER_PERIODIC (1<<17)
94#define APIC_LVT_MASKED (1<<16)
95#define APIC_LVT_LEVEL_TRIGGER (1<<15)
96#define APIC_LVT_REMOTE_IRR (1<<14)
97#define APIC_INPUT_POLARITY (1<<13)
98#define APIC_SEND_PENDING (1<<12)
99#define APIC_MODE_MASK 0x700
100#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
101#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
102#define APIC_MODE_FIXED 0x0
103#define APIC_MODE_NMI 0x4
104#define APIC_MODE_EXTINT 0x7
105#define APIC_LVT1 0x360
106#define APIC_LVTERR 0x370
107#define APIC_TMICT 0x380
108#define APIC_TMCCT 0x390
109#define APIC_TDCR 0x3E0
110#define APIC_TDR_DIV_TMBASE (1<<2)
111#define APIC_TDR_DIV_1 0xB
112#define APIC_TDR_DIV_2 0x0
113#define APIC_TDR_DIV_4 0x1
114#define APIC_TDR_DIV_8 0x2
115#define APIC_TDR_DIV_16 0x3
116#define APIC_TDR_DIV_32 0x8
117#define APIC_TDR_DIV_64 0x9
118#define APIC_TDR_DIV_128 0xA
119#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
120
1#ifdef CONFIG_X86_32 121#ifdef CONFIG_X86_32
2# include "apicdef_32.h" 122# define MAX_IO_APICS 64
3#else 123#else
4# include "apicdef_64.h" 124# define MAX_IO_APICS 128
125# define MAX_LOCAL_APIC 256
126#endif
127
128/*
129 * All x86-64 systems are xAPIC compatible.
130 * In the following, "apicid" is a physical APIC ID.
131 */
132#define XAPIC_DEST_CPUS_SHIFT 4
133#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
134#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
135#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
136#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
137#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
138#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
139
140/*
141 * the local APIC register structure, memory mapped. Not terribly well
142 * tested, but we might eventually use this one in the future - the
143 * problem why we cannot use it right now is the P5 APIC, it has an
144 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
145 */
146#define u32 unsigned int
147
148struct local_apic {
149
150/*000*/ struct { u32 __reserved[4]; } __reserved_01;
151
152/*010*/ struct { u32 __reserved[4]; } __reserved_02;
153
154/*020*/ struct { /* APIC ID Register */
155 u32 __reserved_1 : 24,
156 phys_apic_id : 4,
157 __reserved_2 : 4;
158 u32 __reserved[3];
159 } id;
160
161/*030*/ const
162 struct { /* APIC Version Register */
163 u32 version : 8,
164 __reserved_1 : 8,
165 max_lvt : 8,
166 __reserved_2 : 8;
167 u32 __reserved[3];
168 } version;
169
170/*040*/ struct { u32 __reserved[4]; } __reserved_03;
171
172/*050*/ struct { u32 __reserved[4]; } __reserved_04;
173
174/*060*/ struct { u32 __reserved[4]; } __reserved_05;
175
176/*070*/ struct { u32 __reserved[4]; } __reserved_06;
177
178/*080*/ struct { /* Task Priority Register */
179 u32 priority : 8,
180 __reserved_1 : 24;
181 u32 __reserved_2[3];
182 } tpr;
183
184/*090*/ const
185 struct { /* Arbitration Priority Register */
186 u32 priority : 8,
187 __reserved_1 : 24;
188 u32 __reserved_2[3];
189 } apr;
190
191/*0A0*/ const
192 struct { /* Processor Priority Register */
193 u32 priority : 8,
194 __reserved_1 : 24;
195 u32 __reserved_2[3];
196 } ppr;
197
198/*0B0*/ struct { /* End Of Interrupt Register */
199 u32 eoi;
200 u32 __reserved[3];
201 } eoi;
202
203/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
204
205/*0D0*/ struct { /* Logical Destination Register */
206 u32 __reserved_1 : 24,
207 logical_dest : 8;
208 u32 __reserved_2[3];
209 } ldr;
210
211/*0E0*/ struct { /* Destination Format Register */
212 u32 __reserved_1 : 28,
213 model : 4;
214 u32 __reserved_2[3];
215 } dfr;
216
217/*0F0*/ struct { /* Spurious Interrupt Vector Register */
218 u32 spurious_vector : 8,
219 apic_enabled : 1,
220 focus_cpu : 1,
221 __reserved_2 : 22;
222 u32 __reserved_3[3];
223 } svr;
224
225/*100*/ struct { /* In Service Register */
226/*170*/ u32 bitfield;
227 u32 __reserved[3];
228 } isr [8];
229
230/*180*/ struct { /* Trigger Mode Register */
231/*1F0*/ u32 bitfield;
232 u32 __reserved[3];
233 } tmr [8];
234
235/*200*/ struct { /* Interrupt Request Register */
236/*270*/ u32 bitfield;
237 u32 __reserved[3];
238 } irr [8];
239
240/*280*/ union { /* Error Status Register */
241 struct {
242 u32 send_cs_error : 1,
243 receive_cs_error : 1,
244 send_accept_error : 1,
245 receive_accept_error : 1,
246 __reserved_1 : 1,
247 send_illegal_vector : 1,
248 receive_illegal_vector : 1,
249 illegal_register_address : 1,
250 __reserved_2 : 24;
251 u32 __reserved_3[3];
252 } error_bits;
253 struct {
254 u32 errors;
255 u32 __reserved_3[3];
256 } all_errors;
257 } esr;
258
259/*290*/ struct { u32 __reserved[4]; } __reserved_08;
260
261/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
262
263/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
264
265/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
266
267/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
268
269/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
270
271/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
272
273/*300*/ struct { /* Interrupt Command Register 1 */
274 u32 vector : 8,
275 delivery_mode : 3,
276 destination_mode : 1,
277 delivery_status : 1,
278 __reserved_1 : 1,
279 level : 1,
280 trigger : 1,
281 __reserved_2 : 2,
282 shorthand : 2,
283 __reserved_3 : 12;
284 u32 __reserved_4[3];
285 } icr1;
286
287/*310*/ struct { /* Interrupt Command Register 2 */
288 union {
289 u32 __reserved_1 : 24,
290 phys_dest : 4,
291 __reserved_2 : 4;
292 u32 __reserved_3 : 24,
293 logical_dest : 8;
294 } dest;
295 u32 __reserved_4[3];
296 } icr2;
297
298/*320*/ struct { /* LVT - Timer */
299 u32 vector : 8,
300 __reserved_1 : 4,
301 delivery_status : 1,
302 __reserved_2 : 3,
303 mask : 1,
304 timer_mode : 1,
305 __reserved_3 : 14;
306 u32 __reserved_4[3];
307 } lvt_timer;
308
309/*330*/ struct { /* LVT - Thermal Sensor */
310 u32 vector : 8,
311 delivery_mode : 3,
312 __reserved_1 : 1,
313 delivery_status : 1,
314 __reserved_2 : 3,
315 mask : 1,
316 __reserved_3 : 15;
317 u32 __reserved_4[3];
318 } lvt_thermal;
319
320/*340*/ struct { /* LVT - Performance Counter */
321 u32 vector : 8,
322 delivery_mode : 3,
323 __reserved_1 : 1,
324 delivery_status : 1,
325 __reserved_2 : 3,
326 mask : 1,
327 __reserved_3 : 15;
328 u32 __reserved_4[3];
329 } lvt_pc;
330
331/*350*/ struct { /* LVT - LINT0 */
332 u32 vector : 8,
333 delivery_mode : 3,
334 __reserved_1 : 1,
335 delivery_status : 1,
336 polarity : 1,
337 remote_irr : 1,
338 trigger : 1,
339 mask : 1,
340 __reserved_2 : 15;
341 u32 __reserved_3[3];
342 } lvt_lint0;
343
344/*360*/ struct { /* LVT - LINT1 */
345 u32 vector : 8,
346 delivery_mode : 3,
347 __reserved_1 : 1,
348 delivery_status : 1,
349 polarity : 1,
350 remote_irr : 1,
351 trigger : 1,
352 mask : 1,
353 __reserved_2 : 15;
354 u32 __reserved_3[3];
355 } lvt_lint1;
356
357/*370*/ struct { /* LVT - Error */
358 u32 vector : 8,
359 __reserved_1 : 4,
360 delivery_status : 1,
361 __reserved_2 : 3,
362 mask : 1,
363 __reserved_3 : 15;
364 u32 __reserved_4[3];
365 } lvt_error;
366
367/*380*/ struct { /* Timer Initial Count Register */
368 u32 initial_count;
369 u32 __reserved_2[3];
370 } timer_icr;
371
372/*390*/ const
373 struct { /* Timer Current Count Register */
374 u32 curr_count;
375 u32 __reserved_2[3];
376 } timer_ccr;
377
378/*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
379
380/*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
381
382/*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
383
384/*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
385
386/*3E0*/ struct { /* Timer Divide Configuration Register */
387 u32 divisor : 4,
388 __reserved_1 : 28;
389 u32 __reserved_2[3];
390 } timer_dcr;
391
392/*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
393
394} __attribute__ ((packed));
395
396#undef u32
397
398#define BAD_APICID 0xFFu
399
5#endif 400#endif
diff --git a/include/asm-x86/apicdef_32.h b/include/asm-x86/apicdef_32.h
deleted file mode 100644
index 9f6995341fdc..000000000000
--- a/include/asm-x86/apicdef_32.h
+++ /dev/null
@@ -1,375 +0,0 @@
1#ifndef __ASM_APICDEF_H
2#define __ASM_APICDEF_H
3
4/*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
10
11#define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13#define APIC_ID 0x20
14#define APIC_LVR 0x30
15#define APIC_LVR_MASK 0xFF00FF
16#define GET_APIC_VERSION(x) ((x)&0xFF)
17#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
18#define APIC_INTEGRATED(x) ((x)&0xF0)
19#define APIC_XAPIC(x) ((x) >= 0x14)
20#define APIC_TASKPRI 0x80
21#define APIC_TPRI_MASK 0xFF
22#define APIC_ARBPRI 0x90
23#define APIC_ARBPRI_MASK 0xFF
24#define APIC_PROCPRI 0xA0
25#define APIC_EOI 0xB0
26#define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
27#define APIC_RRR 0xC0
28#define APIC_LDR 0xD0
29#define APIC_LDR_MASK (0xFF<<24)
30#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
31#define SET_APIC_LOGICAL_ID(x) (((x)<<24))
32#define APIC_ALL_CPUS 0xFF
33#define APIC_DFR 0xE0
34#define APIC_DFR_CLUSTER 0x0FFFFFFFul
35#define APIC_DFR_FLAT 0xFFFFFFFFul
36#define APIC_SPIV 0xF0
37#define APIC_SPIV_FOCUS_DISABLED (1<<9)
38#define APIC_SPIV_APIC_ENABLED (1<<8)
39#define APIC_ISR 0x100
40#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
41#define APIC_TMR 0x180
42#define APIC_IRR 0x200
43#define APIC_ESR 0x280
44#define APIC_ESR_SEND_CS 0x00001
45#define APIC_ESR_RECV_CS 0x00002
46#define APIC_ESR_SEND_ACC 0x00004
47#define APIC_ESR_RECV_ACC 0x00008
48#define APIC_ESR_SENDILL 0x00020
49#define APIC_ESR_RECVILL 0x00040
50#define APIC_ESR_ILLREGA 0x00080
51#define APIC_ICR 0x300
52#define APIC_DEST_SELF 0x40000
53#define APIC_DEST_ALLINC 0x80000
54#define APIC_DEST_ALLBUT 0xC0000
55#define APIC_ICR_RR_MASK 0x30000
56#define APIC_ICR_RR_INVALID 0x00000
57#define APIC_ICR_RR_INPROG 0x10000
58#define APIC_ICR_RR_VALID 0x20000
59#define APIC_INT_LEVELTRIG 0x08000
60#define APIC_INT_ASSERT 0x04000
61#define APIC_ICR_BUSY 0x01000
62#define APIC_DEST_LOGICAL 0x00800
63#define APIC_DM_FIXED 0x00000
64#define APIC_DM_LOWEST 0x00100
65#define APIC_DM_SMI 0x00200
66#define APIC_DM_REMRD 0x00300
67#define APIC_DM_NMI 0x00400
68#define APIC_DM_INIT 0x00500
69#define APIC_DM_STARTUP 0x00600
70#define APIC_DM_EXTINT 0x00700
71#define APIC_VECTOR_MASK 0x000FF
72#define APIC_ICR2 0x310
73#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
74#define SET_APIC_DEST_FIELD(x) ((x)<<24)
75#define APIC_LVTT 0x320
76#define APIC_LVTTHMR 0x330
77#define APIC_LVTPC 0x340
78#define APIC_LVT0 0x350
79#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
80#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
81#define SET_APIC_TIMER_BASE(x) (((x)<<18))
82#define APIC_TIMER_BASE_CLKIN 0x0
83#define APIC_TIMER_BASE_TMBASE 0x1
84#define APIC_TIMER_BASE_DIV 0x2
85#define APIC_LVT_TIMER_PERIODIC (1<<17)
86#define APIC_LVT_MASKED (1<<16)
87#define APIC_LVT_LEVEL_TRIGGER (1<<15)
88#define APIC_LVT_REMOTE_IRR (1<<14)
89#define APIC_INPUT_POLARITY (1<<13)
90#define APIC_SEND_PENDING (1<<12)
91#define APIC_MODE_MASK 0x700
92#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
93#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
94#define APIC_MODE_FIXED 0x0
95#define APIC_MODE_NMI 0x4
96#define APIC_MODE_EXTINT 0x7
97#define APIC_LVT1 0x360
98#define APIC_LVTERR 0x370
99#define APIC_TMICT 0x380
100#define APIC_TMCCT 0x390
101#define APIC_TDCR 0x3E0
102#define APIC_TDR_DIV_TMBASE (1<<2)
103#define APIC_TDR_DIV_1 0xB
104#define APIC_TDR_DIV_2 0x0
105#define APIC_TDR_DIV_4 0x1
106#define APIC_TDR_DIV_8 0x2
107#define APIC_TDR_DIV_16 0x3
108#define APIC_TDR_DIV_32 0x8
109#define APIC_TDR_DIV_64 0x9
110#define APIC_TDR_DIV_128 0xA
111
112#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
113
114#define MAX_IO_APICS 64
115
116/*
117 * the local APIC register structure, memory mapped. Not terribly well
118 * tested, but we might eventually use this one in the future - the
119 * problem why we cannot use it right now is the P5 APIC, it has an
120 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
121 */
122#define u32 unsigned int
123
124
125struct local_apic {
126
127/*000*/ struct { u32 __reserved[4]; } __reserved_01;
128
129/*010*/ struct { u32 __reserved[4]; } __reserved_02;
130
131/*020*/ struct { /* APIC ID Register */
132 u32 __reserved_1 : 24,
133 phys_apic_id : 4,
134 __reserved_2 : 4;
135 u32 __reserved[3];
136 } id;
137
138/*030*/ const
139 struct { /* APIC Version Register */
140 u32 version : 8,
141 __reserved_1 : 8,
142 max_lvt : 8,
143 __reserved_2 : 8;
144 u32 __reserved[3];
145 } version;
146
147/*040*/ struct { u32 __reserved[4]; } __reserved_03;
148
149/*050*/ struct { u32 __reserved[4]; } __reserved_04;
150
151/*060*/ struct { u32 __reserved[4]; } __reserved_05;
152
153/*070*/ struct { u32 __reserved[4]; } __reserved_06;
154
155/*080*/ struct { /* Task Priority Register */
156 u32 priority : 8,
157 __reserved_1 : 24;
158 u32 __reserved_2[3];
159 } tpr;
160
161/*090*/ const
162 struct { /* Arbitration Priority Register */
163 u32 priority : 8,
164 __reserved_1 : 24;
165 u32 __reserved_2[3];
166 } apr;
167
168/*0A0*/ const
169 struct { /* Processor Priority Register */
170 u32 priority : 8,
171 __reserved_1 : 24;
172 u32 __reserved_2[3];
173 } ppr;
174
175/*0B0*/ struct { /* End Of Interrupt Register */
176 u32 eoi;
177 u32 __reserved[3];
178 } eoi;
179
180/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
181
182/*0D0*/ struct { /* Logical Destination Register */
183 u32 __reserved_1 : 24,
184 logical_dest : 8;
185 u32 __reserved_2[3];
186 } ldr;
187
188/*0E0*/ struct { /* Destination Format Register */
189 u32 __reserved_1 : 28,
190 model : 4;
191 u32 __reserved_2[3];
192 } dfr;
193
194/*0F0*/ struct { /* Spurious Interrupt Vector Register */
195 u32 spurious_vector : 8,
196 apic_enabled : 1,
197 focus_cpu : 1,
198 __reserved_2 : 22;
199 u32 __reserved_3[3];
200 } svr;
201
202/*100*/ struct { /* In Service Register */
203/*170*/ u32 bitfield;
204 u32 __reserved[3];
205 } isr [8];
206
207/*180*/ struct { /* Trigger Mode Register */
208/*1F0*/ u32 bitfield;
209 u32 __reserved[3];
210 } tmr [8];
211
212/*200*/ struct { /* Interrupt Request Register */
213/*270*/ u32 bitfield;
214 u32 __reserved[3];
215 } irr [8];
216
217/*280*/ union { /* Error Status Register */
218 struct {
219 u32 send_cs_error : 1,
220 receive_cs_error : 1,
221 send_accept_error : 1,
222 receive_accept_error : 1,
223 __reserved_1 : 1,
224 send_illegal_vector : 1,
225 receive_illegal_vector : 1,
226 illegal_register_address : 1,
227 __reserved_2 : 24;
228 u32 __reserved_3[3];
229 } error_bits;
230 struct {
231 u32 errors;
232 u32 __reserved_3[3];
233 } all_errors;
234 } esr;
235
236/*290*/ struct { u32 __reserved[4]; } __reserved_08;
237
238/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
239
240/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
241
242/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
243
244/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
245
246/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
247
248/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
249
250/*300*/ struct { /* Interrupt Command Register 1 */
251 u32 vector : 8,
252 delivery_mode : 3,
253 destination_mode : 1,
254 delivery_status : 1,
255 __reserved_1 : 1,
256 level : 1,
257 trigger : 1,
258 __reserved_2 : 2,
259 shorthand : 2,
260 __reserved_3 : 12;
261 u32 __reserved_4[3];
262 } icr1;
263
264/*310*/ struct { /* Interrupt Command Register 2 */
265 union {
266 u32 __reserved_1 : 24,
267 phys_dest : 4,
268 __reserved_2 : 4;
269 u32 __reserved_3 : 24,
270 logical_dest : 8;
271 } dest;
272 u32 __reserved_4[3];
273 } icr2;
274
275/*320*/ struct { /* LVT - Timer */
276 u32 vector : 8,
277 __reserved_1 : 4,
278 delivery_status : 1,
279 __reserved_2 : 3,
280 mask : 1,
281 timer_mode : 1,
282 __reserved_3 : 14;
283 u32 __reserved_4[3];
284 } lvt_timer;
285
286/*330*/ struct { /* LVT - Thermal Sensor */
287 u32 vector : 8,
288 delivery_mode : 3,
289 __reserved_1 : 1,
290 delivery_status : 1,
291 __reserved_2 : 3,
292 mask : 1,
293 __reserved_3 : 15;
294 u32 __reserved_4[3];
295 } lvt_thermal;
296
297/*340*/ struct { /* LVT - Performance Counter */
298 u32 vector : 8,
299 delivery_mode : 3,
300 __reserved_1 : 1,
301 delivery_status : 1,
302 __reserved_2 : 3,
303 mask : 1,
304 __reserved_3 : 15;
305 u32 __reserved_4[3];
306 } lvt_pc;
307
308/*350*/ struct { /* LVT - LINT0 */
309 u32 vector : 8,
310 delivery_mode : 3,
311 __reserved_1 : 1,
312 delivery_status : 1,
313 polarity : 1,
314 remote_irr : 1,
315 trigger : 1,
316 mask : 1,
317 __reserved_2 : 15;
318 u32 __reserved_3[3];
319 } lvt_lint0;
320
321/*360*/ struct { /* LVT - LINT1 */
322 u32 vector : 8,
323 delivery_mode : 3,
324 __reserved_1 : 1,
325 delivery_status : 1,
326 polarity : 1,
327 remote_irr : 1,
328 trigger : 1,
329 mask : 1,
330 __reserved_2 : 15;
331 u32 __reserved_3[3];
332 } lvt_lint1;
333
334/*370*/ struct { /* LVT - Error */
335 u32 vector : 8,
336 __reserved_1 : 4,
337 delivery_status : 1,
338 __reserved_2 : 3,
339 mask : 1,
340 __reserved_3 : 15;
341 u32 __reserved_4[3];
342 } lvt_error;
343
344/*380*/ struct { /* Timer Initial Count Register */
345 u32 initial_count;
346 u32 __reserved_2[3];
347 } timer_icr;
348
349/*390*/ const
350 struct { /* Timer Current Count Register */
351 u32 curr_count;
352 u32 __reserved_2[3];
353 } timer_ccr;
354
355/*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
356
357/*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
358
359/*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
360
361/*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
362
363/*3E0*/ struct { /* Timer Divide Configuration Register */
364 u32 divisor : 4,
365 __reserved_1 : 28;
366 u32 __reserved_2[3];
367 } timer_dcr;
368
369/*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
370
371} __attribute__ ((packed));
372
373#undef u32
374
375#endif
diff --git a/include/asm-x86/apicdef_64.h b/include/asm-x86/apicdef_64.h
deleted file mode 100644
index 1dd40067c67c..000000000000
--- a/include/asm-x86/apicdef_64.h
+++ /dev/null
@@ -1,392 +0,0 @@
1#ifndef __ASM_APICDEF_H
2#define __ASM_APICDEF_H
3
4/*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
10
11#define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13#define APIC_ID 0x20
14#define APIC_ID_MASK (0xFFu<<24)
15#define GET_APIC_ID(x) (((x)>>24)&0xFFu)
16#define SET_APIC_ID(x) (((x)<<24))
17#define APIC_LVR 0x30
18#define APIC_LVR_MASK 0xFF00FF
19#define GET_APIC_VERSION(x) ((x)&0xFFu)
20#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu)
21#define APIC_INTEGRATED(x) ((x)&0xF0u)
22#define APIC_TASKPRI 0x80
23#define APIC_TPRI_MASK 0xFFu
24#define APIC_ARBPRI 0x90
25#define APIC_ARBPRI_MASK 0xFFu
26#define APIC_PROCPRI 0xA0
27#define APIC_EOI 0xB0
28#define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
29#define APIC_RRR 0xC0
30#define APIC_LDR 0xD0
31#define APIC_LDR_MASK (0xFFu<<24)
32#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu)
33#define SET_APIC_LOGICAL_ID(x) (((x)<<24))
34#define APIC_ALL_CPUS 0xFFu
35#define APIC_DFR 0xE0
36#define APIC_DFR_CLUSTER 0x0FFFFFFFul
37#define APIC_DFR_FLAT 0xFFFFFFFFul
38#define APIC_SPIV 0xF0
39#define APIC_SPIV_FOCUS_DISABLED (1<<9)
40#define APIC_SPIV_APIC_ENABLED (1<<8)
41#define APIC_ISR 0x100
42#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
43#define APIC_TMR 0x180
44#define APIC_IRR 0x200
45#define APIC_ESR 0x280
46#define APIC_ESR_SEND_CS 0x00001
47#define APIC_ESR_RECV_CS 0x00002
48#define APIC_ESR_SEND_ACC 0x00004
49#define APIC_ESR_RECV_ACC 0x00008
50#define APIC_ESR_SENDILL 0x00020
51#define APIC_ESR_RECVILL 0x00040
52#define APIC_ESR_ILLREGA 0x00080
53#define APIC_ICR 0x300
54#define APIC_DEST_SELF 0x40000
55#define APIC_DEST_ALLINC 0x80000
56#define APIC_DEST_ALLBUT 0xC0000
57#define APIC_ICR_RR_MASK 0x30000
58#define APIC_ICR_RR_INVALID 0x00000
59#define APIC_ICR_RR_INPROG 0x10000
60#define APIC_ICR_RR_VALID 0x20000
61#define APIC_INT_LEVELTRIG 0x08000
62#define APIC_INT_ASSERT 0x04000
63#define APIC_ICR_BUSY 0x01000
64#define APIC_DEST_LOGICAL 0x00800
65#define APIC_DEST_PHYSICAL 0x00000
66#define APIC_DM_FIXED 0x00000
67#define APIC_DM_LOWEST 0x00100
68#define APIC_DM_SMI 0x00200
69#define APIC_DM_REMRD 0x00300
70#define APIC_DM_NMI 0x00400
71#define APIC_DM_INIT 0x00500
72#define APIC_DM_STARTUP 0x00600
73#define APIC_DM_EXTINT 0x00700
74#define APIC_VECTOR_MASK 0x000FF
75#define APIC_ICR2 0x310
76#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
77#define SET_APIC_DEST_FIELD(x) ((x)<<24)
78#define APIC_LVTT 0x320
79#define APIC_LVTTHMR 0x330
80#define APIC_LVTPC 0x340
81#define APIC_LVT0 0x350
82#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
83#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
84#define SET_APIC_TIMER_BASE(x) (((x)<<18))
85#define APIC_TIMER_BASE_CLKIN 0x0
86#define APIC_TIMER_BASE_TMBASE 0x1
87#define APIC_TIMER_BASE_DIV 0x2
88#define APIC_LVT_TIMER_PERIODIC (1<<17)
89#define APIC_LVT_MASKED (1<<16)
90#define APIC_LVT_LEVEL_TRIGGER (1<<15)
91#define APIC_LVT_REMOTE_IRR (1<<14)
92#define APIC_INPUT_POLARITY (1<<13)
93#define APIC_SEND_PENDING (1<<12)
94#define APIC_MODE_MASK 0x700
95#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
96#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
97#define APIC_MODE_FIXED 0x0
98#define APIC_MODE_NMI 0x4
99#define APIC_MODE_EXTINT 0x7
100#define APIC_LVT1 0x360
101#define APIC_LVTERR 0x370
102#define APIC_TMICT 0x380
103#define APIC_TMCCT 0x390
104#define APIC_TDCR 0x3E0
105#define APIC_TDR_DIV_TMBASE (1<<2)
106#define APIC_TDR_DIV_1 0xB
107#define APIC_TDR_DIV_2 0x0
108#define APIC_TDR_DIV_4 0x1
109#define APIC_TDR_DIV_8 0x2
110#define APIC_TDR_DIV_16 0x3
111#define APIC_TDR_DIV_32 0x8
112#define APIC_TDR_DIV_64 0x9
113#define APIC_TDR_DIV_128 0xA
114
115#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
116
117#define MAX_IO_APICS 128
118#define MAX_LOCAL_APIC 256
119
120/*
121 * All x86-64 systems are xAPIC compatible.
122 * In the following, "apicid" is a physical APIC ID.
123 */
124#define XAPIC_DEST_CPUS_SHIFT 4
125#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
126#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
127#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
128#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
129#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
130#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
131
132/*
133 * the local APIC register structure, memory mapped. Not terribly well
134 * tested, but we might eventually use this one in the future - the
135 * problem why we cannot use it right now is the P5 APIC, it has an
136 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
137 */
138#define u32 unsigned int
139
140struct local_apic {
141
142/*000*/ struct { u32 __reserved[4]; } __reserved_01;
143
144/*010*/ struct { u32 __reserved[4]; } __reserved_02;
145
146/*020*/ struct { /* APIC ID Register */
147 u32 __reserved_1 : 24,
148 phys_apic_id : 4,
149 __reserved_2 : 4;
150 u32 __reserved[3];
151 } id;
152
153/*030*/ const
154 struct { /* APIC Version Register */
155 u32 version : 8,
156 __reserved_1 : 8,
157 max_lvt : 8,
158 __reserved_2 : 8;
159 u32 __reserved[3];
160 } version;
161
162/*040*/ struct { u32 __reserved[4]; } __reserved_03;
163
164/*050*/ struct { u32 __reserved[4]; } __reserved_04;
165
166/*060*/ struct { u32 __reserved[4]; } __reserved_05;
167
168/*070*/ struct { u32 __reserved[4]; } __reserved_06;
169
170/*080*/ struct { /* Task Priority Register */
171 u32 priority : 8,
172 __reserved_1 : 24;
173 u32 __reserved_2[3];
174 } tpr;
175
176/*090*/ const
177 struct { /* Arbitration Priority Register */
178 u32 priority : 8,
179 __reserved_1 : 24;
180 u32 __reserved_2[3];
181 } apr;
182
183/*0A0*/ const
184 struct { /* Processor Priority Register */
185 u32 priority : 8,
186 __reserved_1 : 24;
187 u32 __reserved_2[3];
188 } ppr;
189
190/*0B0*/ struct { /* End Of Interrupt Register */
191 u32 eoi;
192 u32 __reserved[3];
193 } eoi;
194
195/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
196
197/*0D0*/ struct { /* Logical Destination Register */
198 u32 __reserved_1 : 24,
199 logical_dest : 8;
200 u32 __reserved_2[3];
201 } ldr;
202
203/*0E0*/ struct { /* Destination Format Register */
204 u32 __reserved_1 : 28,
205 model : 4;
206 u32 __reserved_2[3];
207 } dfr;
208
209/*0F0*/ struct { /* Spurious Interrupt Vector Register */
210 u32 spurious_vector : 8,
211 apic_enabled : 1,
212 focus_cpu : 1,
213 __reserved_2 : 22;
214 u32 __reserved_3[3];
215 } svr;
216
217/*100*/ struct { /* In Service Register */
218/*170*/ u32 bitfield;
219 u32 __reserved[3];
220 } isr [8];
221
222/*180*/ struct { /* Trigger Mode Register */
223/*1F0*/ u32 bitfield;
224 u32 __reserved[3];
225 } tmr [8];
226
227/*200*/ struct { /* Interrupt Request Register */
228/*270*/ u32 bitfield;
229 u32 __reserved[3];
230 } irr [8];
231
232/*280*/ union { /* Error Status Register */
233 struct {
234 u32 send_cs_error : 1,
235 receive_cs_error : 1,
236 send_accept_error : 1,
237 receive_accept_error : 1,
238 __reserved_1 : 1,
239 send_illegal_vector : 1,
240 receive_illegal_vector : 1,
241 illegal_register_address : 1,
242 __reserved_2 : 24;
243 u32 __reserved_3[3];
244 } error_bits;
245 struct {
246 u32 errors;
247 u32 __reserved_3[3];
248 } all_errors;
249 } esr;
250
251/*290*/ struct { u32 __reserved[4]; } __reserved_08;
252
253/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
254
255/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
256
257/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
258
259/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
260
261/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
262
263/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
264
265/*300*/ struct { /* Interrupt Command Register 1 */
266 u32 vector : 8,
267 delivery_mode : 3,
268 destination_mode : 1,
269 delivery_status : 1,
270 __reserved_1 : 1,
271 level : 1,
272 trigger : 1,
273 __reserved_2 : 2,
274 shorthand : 2,
275 __reserved_3 : 12;
276 u32 __reserved_4[3];
277 } icr1;
278
279/*310*/ struct { /* Interrupt Command Register 2 */
280 union {
281 u32 __reserved_1 : 24,
282 phys_dest : 4,
283 __reserved_2 : 4;
284 u32 __reserved_3 : 24,
285 logical_dest : 8;
286 } dest;
287 u32 __reserved_4[3];
288 } icr2;
289
290/*320*/ struct { /* LVT - Timer */
291 u32 vector : 8,
292 __reserved_1 : 4,
293 delivery_status : 1,
294 __reserved_2 : 3,
295 mask : 1,
296 timer_mode : 1,
297 __reserved_3 : 14;
298 u32 __reserved_4[3];
299 } lvt_timer;
300
301/*330*/ struct { /* LVT - Thermal Sensor */
302 u32 vector : 8,
303 delivery_mode : 3,
304 __reserved_1 : 1,
305 delivery_status : 1,
306 __reserved_2 : 3,
307 mask : 1,
308 __reserved_3 : 15;
309 u32 __reserved_4[3];
310 } lvt_thermal;
311
312/*340*/ struct { /* LVT - Performance Counter */
313 u32 vector : 8,
314 delivery_mode : 3,
315 __reserved_1 : 1,
316 delivery_status : 1,
317 __reserved_2 : 3,
318 mask : 1,
319 __reserved_3 : 15;
320 u32 __reserved_4[3];
321 } lvt_pc;
322
323/*350*/ struct { /* LVT - LINT0 */
324 u32 vector : 8,
325 delivery_mode : 3,
326 __reserved_1 : 1,
327 delivery_status : 1,
328 polarity : 1,
329 remote_irr : 1,
330 trigger : 1,
331 mask : 1,
332 __reserved_2 : 15;
333 u32 __reserved_3[3];
334 } lvt_lint0;
335
336/*360*/ struct { /* LVT - LINT1 */
337 u32 vector : 8,
338 delivery_mode : 3,
339 __reserved_1 : 1,
340 delivery_status : 1,
341 polarity : 1,
342 remote_irr : 1,
343 trigger : 1,
344 mask : 1,
345 __reserved_2 : 15;
346 u32 __reserved_3[3];
347 } lvt_lint1;
348
349/*370*/ struct { /* LVT - Error */
350 u32 vector : 8,
351 __reserved_1 : 4,
352 delivery_status : 1,
353 __reserved_2 : 3,
354 mask : 1,
355 __reserved_3 : 15;
356 u32 __reserved_4[3];
357 } lvt_error;
358
359/*380*/ struct { /* Timer Initial Count Register */
360 u32 initial_count;
361 u32 __reserved_2[3];
362 } timer_icr;
363
364/*390*/ const
365 struct { /* Timer Current Count Register */
366 u32 curr_count;
367 u32 __reserved_2[3];
368 } timer_ccr;
369
370/*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
371
372/*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
373
374/*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
375
376/*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
377
378/*3E0*/ struct { /* Timer Divide Configuration Register */
379 u32 divisor : 4,
380 __reserved_1 : 28;
381 u32 __reserved_2[3];
382 } timer_dcr;
383
384/*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
385
386} __attribute__ ((packed));
387
388#undef u32
389
390#define BAD_APICID 0xFFu
391
392#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 01:45:03 -0500