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authorThomas Gleixner <tglx@linutronix.de>2007-10-15 17:28:19 -0400
committerThomas Gleixner <tglx@inhelltoy.tec.linutronix.de>2007-10-17 14:17:12 -0400
commit17d36707dd9c5c3c4ef09a278ee7444cfc60481e (patch)
treea5ca7943eae2caeaaa1554a5b3a04d01dad87953 /include/asm-x86
parent003a46cfff308ee0d879dfa89b9a7c65b2a481bf (diff)
x86: unify include/asm/agp_32/64.h
Same file, except for whitespace, comment formatting and the usage of wbinvd() instead of asm volatile("wbinvd":::"memory"), which is the same. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/agp.h43
-rw-r--r--include/asm-x86/agp_32.h36
-rw-r--r--include/asm-x86/agp_64.h34
3 files changed, 39 insertions, 74 deletions
diff --git a/include/asm-x86/agp.h b/include/asm-x86/agp.h
index 9348f1e4f6f1..62df2a9e7130 100644
--- a/include/asm-x86/agp.h
+++ b/include/asm-x86/agp.h
@@ -1,5 +1,40 @@
1#ifdef CONFIG_X86_32 1#ifndef _ASM_X86_AGP_H
2# include "agp_32.h" 2#define _ASM_X86_AGP_H
3#else 3
4# include "agp_64.h" 4#include <asm/pgtable.h>
5#include <asm/cacheflush.h>
6
7/*
8 * Functions to keep the agpgart mappings coherent with the MMU. The
9 * GART gives the CPU a physical alias of pages in memory. The alias
10 * region is mapped uncacheable. Make sure there are no conflicting
11 * mappings with different cachability attributes for the same
12 * page. This avoids data corruption on some CPUs.
13 */
14
15/*
16 * Caller's responsibility to call global_flush_tlb() for performance
17 * reasons
18 */
19#define map_page_into_agp(page) change_page_attr(page, 1, PAGE_KERNEL_NOCACHE)
20#define unmap_page_from_agp(page) change_page_attr(page, 1, PAGE_KERNEL)
21#define flush_agp_mappings() global_flush_tlb()
22
23/*
24 * Could use CLFLUSH here if the cpu supports it. But then it would
25 * need to be called for each cacheline of the whole page so it may
26 * not be worth it. Would need a page for it.
27 */
28#define flush_agp_cache() wbinvd()
29
30/* Convert a physical address to an address suitable for the GART. */
31#define phys_to_gart(x) (x)
32#define gart_to_phys(x) (x)
33
34/* GATT allocation. Returns/accepts GATT kernel virtual address. */
35#define alloc_gatt_pages(order) \
36 ((char *)__get_free_pages(GFP_KERNEL, (order)))
37#define free_gatt_pages(table, order) \
38 free_pages((unsigned long)(table), (order))
39
5#endif 40#endif
diff --git a/include/asm-x86/agp_32.h b/include/asm-x86/agp_32.h
deleted file mode 100644
index 6af173dbf123..000000000000
--- a/include/asm-x86/agp_32.h
+++ /dev/null
@@ -1,36 +0,0 @@
1#ifndef AGP_H
2#define AGP_H 1
3
4#include <asm/pgtable.h>
5#include <asm/cacheflush.h>
6
7/*
8 * Functions to keep the agpgart mappings coherent with the MMU.
9 * The GART gives the CPU a physical alias of pages in memory. The alias region is
10 * mapped uncacheable. Make sure there are no conflicting mappings
11 * with different cachability attributes for the same page. This avoids
12 * data corruption on some CPUs.
13 */
14
15/* Caller's responsibility to call global_flush_tlb() for
16 * performance reasons */
17#define map_page_into_agp(page) change_page_attr(page, 1, PAGE_KERNEL_NOCACHE)
18#define unmap_page_from_agp(page) change_page_attr(page, 1, PAGE_KERNEL)
19#define flush_agp_mappings() global_flush_tlb()
20
21/* Could use CLFLUSH here if the cpu supports it. But then it would
22 need to be called for each cacheline of the whole page so it may not be
23 worth it. Would need a page for it. */
24#define flush_agp_cache() wbinvd()
25
26/* Convert a physical address to an address suitable for the GART. */
27#define phys_to_gart(x) (x)
28#define gart_to_phys(x) (x)
29
30/* GATT allocation. Returns/accepts GATT kernel virtual address. */
31#define alloc_gatt_pages(order) \
32 ((char *)__get_free_pages(GFP_KERNEL, (order)))
33#define free_gatt_pages(table, order) \
34 free_pages((unsigned long)(table), (order))
35
36#endif
diff --git a/include/asm-x86/agp_64.h b/include/asm-x86/agp_64.h
deleted file mode 100644
index de338666f3f9..000000000000
--- a/include/asm-x86/agp_64.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef AGP_H
2#define AGP_H 1
3
4#include <asm/cacheflush.h>
5
6/*
7 * Functions to keep the agpgart mappings coherent.
8 * The GART gives the CPU a physical alias of memory. The alias is
9 * mapped uncacheable. Make sure there are no conflicting mappings
10 * with different cachability attributes for the same page.
11 */
12
13/* Caller's responsibility to call global_flush_tlb() for
14 * performance reasons */
15#define map_page_into_agp(page) change_page_attr(page, 1, PAGE_KERNEL_NOCACHE)
16#define unmap_page_from_agp(page) change_page_attr(page, 1, PAGE_KERNEL)
17#define flush_agp_mappings() global_flush_tlb()
18
19/* Could use CLFLUSH here if the cpu supports it. But then it would
20 need to be called for each cacheline of the whole page so it may not be
21 worth it. Would need a page for it. */
22#define flush_agp_cache() asm volatile("wbinvd":::"memory")
23
24/* Convert a physical address to an address suitable for the GART. */
25#define phys_to_gart(x) (x)
26#define gart_to_phys(x) (x)
27
28/* GATT allocation. Returns/accepts GATT kernel virtual address. */
29#define alloc_gatt_pages(order) \
30 ((char *)__get_free_pages(GFP_KERNEL, (order)))
31#define free_gatt_pages(table, order) \
32 free_pages((unsigned long)(table), (order))
33
34#endif