diff options
author | Jack Steiner <steiner@sgi.com> | 2008-03-28 15:12:13 -0400 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-04-17 11:41:33 -0400 |
commit | 952cf6d7ae52cc5423baa57e978e20e732a89ba6 (patch) | |
tree | e0d6d076199c4b9e7cda10af4612d12f443a5102 /include/asm-x86/uv | |
parent | 0d3e865b2644e4a2250ab25c5475a0cd0d514b7e (diff) |
x86: define the macros and tables for the basic UV infrastructure.
Define the macros and tables for the basic UV infrastructure.
Signed-off-by: Jack Steiner <steiner@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/uv')
-rw-r--r-- | include/asm-x86/uv/uv_hub.h | 210 |
1 files changed, 210 insertions, 0 deletions
diff --git a/include/asm-x86/uv/uv_hub.h b/include/asm-x86/uv/uv_hub.h new file mode 100644 index 000000000000..b4fcf9cf8951 --- /dev/null +++ b/include/asm-x86/uv/uv_hub.h | |||
@@ -0,0 +1,210 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * SGI UV architectural definitions | ||
7 | * | ||
8 | * Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_X86_UV_HUB_H__ | ||
12 | #define __ASM_X86_UV_HUB_H__ | ||
13 | |||
14 | #include <linux/numa.h> | ||
15 | #include <linux/percpu.h> | ||
16 | #include <asm/types.h> | ||
17 | #include <asm/percpu.h> | ||
18 | |||
19 | |||
20 | /* | ||
21 | * Addressing Terminology | ||
22 | * | ||
23 | * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of | ||
24 | * routers always have low bit of 1, C/MBricks have low bit | ||
25 | * equal to 0. Most addressing macros that target UV hub chips | ||
26 | * right shift the NASID by 1 to exclude the always-zero bit. | ||
27 | * | ||
28 | * SNASID - NASID right shifted by 1 bit. | ||
29 | * | ||
30 | * | ||
31 | * Memory/UV-HUB Processor Socket Address Format: | ||
32 | * +--------+---------------+---------------------+ | ||
33 | * |00..0000| SNASID | NodeOffset | | ||
34 | * +--------+---------------+---------------------+ | ||
35 | * <--- N bits --->|<--------M bits -----> | ||
36 | * | ||
37 | * M number of node offset bits (35 .. 40) | ||
38 | * N number of SNASID bits (0 .. 10) | ||
39 | * | ||
40 | * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). | ||
41 | * The actual values are configuration dependent and are set at | ||
42 | * boot time | ||
43 | * | ||
44 | * APICID format | ||
45 | * NOTE!!!!!! This is the current format of the APICID. However, code | ||
46 | * should assume that this will change in the future. Use functions | ||
47 | * in this file for all APICID bit manipulations and conversion. | ||
48 | * | ||
49 | * 1111110000000000 | ||
50 | * 5432109876543210 | ||
51 | * nnnnnnnnnnlc0cch | ||
52 | * sssssssssss | ||
53 | * | ||
54 | * n = snasid bits | ||
55 | * l = socket number on board | ||
56 | * c = core | ||
57 | * h = hyperthread | ||
58 | * s = bits that are in the socket CSR | ||
59 | * | ||
60 | * Note: Processor only supports 12 bits in the APICID register. The ACPI | ||
61 | * tables hold all 16 bits. Software needs to be aware of this. | ||
62 | * | ||
63 | * Unless otherwise specified, all references to APICID refer to | ||
64 | * the FULL value contained in ACPI tables, not the subset in the | ||
65 | * processor APICID register. | ||
66 | */ | ||
67 | |||
68 | |||
69 | /* | ||
70 | * Maximum number of bricks in all partitions and in all coherency domains. | ||
71 | * This is the total number of bricks accessible in the numalink fabric. It | ||
72 | * includes all C & M bricks. Routers are NOT included. | ||
73 | * | ||
74 | * This value is also the value of the maximum number of non-router NASIDs | ||
75 | * in the numalink fabric. | ||
76 | * | ||
77 | * NOTE: a brick may be 1 or 2 OS nodes. Don't get these confused. | ||
78 | */ | ||
79 | #define UV_MAX_NUMALINK_BLADES 16384 | ||
80 | |||
81 | /* | ||
82 | * Maximum number of C/Mbricks within a software SSI (hardware may support | ||
83 | * more). | ||
84 | */ | ||
85 | #define UV_MAX_SSI_BLADES 256 | ||
86 | |||
87 | /* | ||
88 | * The largest possible NASID of a C or M brick (+ 2) | ||
89 | */ | ||
90 | #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) | ||
91 | |||
92 | /* | ||
93 | * The following defines attributes of the HUB chip. These attributes are | ||
94 | * frequently referenced and are kept in the per-cpu data areas of each cpu. | ||
95 | * They are kept together in a struct to minimize cache misses. | ||
96 | */ | ||
97 | struct uv_hub_info_s { | ||
98 | unsigned long global_mmr_base; | ||
99 | unsigned short local_nasid; | ||
100 | unsigned short gnode_upper; | ||
101 | unsigned short coherency_domain_number; | ||
102 | unsigned short numa_blade_id; | ||
103 | unsigned char blade_processor_id; | ||
104 | unsigned char m_val; | ||
105 | unsigned char n_val; | ||
106 | }; | ||
107 | DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); | ||
108 | #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) | ||
109 | #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) | ||
110 | |||
111 | /* | ||
112 | * Local & Global MMR space macros. | ||
113 | * Note: macros are intended to be used ONLY by inline functions | ||
114 | * in this file - not by other kernel code. | ||
115 | */ | ||
116 | #define UV_SNASID(n) ((n) >> 1) | ||
117 | #define UV_NASID(n) ((n) << 1) | ||
118 | |||
119 | #define UV_LOCAL_MMR_BASE 0xf4000000UL | ||
120 | #define UV_GLOBAL_MMR32_BASE 0xf8000000UL | ||
121 | #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) | ||
122 | |||
123 | #define UV_GLOBAL_MMR32_SNASID_MASK 0x3ff | ||
124 | #define UV_GLOBAL_MMR32_SNASID_SHIFT 15 | ||
125 | #define UV_GLOBAL_MMR64_SNASID_SHIFT 26 | ||
126 | |||
127 | #define UV_GLOBAL_MMR32_NASID_BITS(n) \ | ||
128 | (((UV_SNASID(n) & UV_GLOBAL_MMR32_SNASID_MASK)) << \ | ||
129 | (UV_GLOBAL_MMR32_SNASID_SHIFT)) | ||
130 | |||
131 | #define UV_GLOBAL_MMR64_NASID_BITS(n) \ | ||
132 | ((unsigned long)UV_SNASID(n) << UV_GLOBAL_MMR64_SNASID_SHIFT) | ||
133 | |||
134 | #define UV_APIC_NASID_SHIFT 6 | ||
135 | |||
136 | /* | ||
137 | * Extract a NASID from an APICID (full apicid, not processor subset) | ||
138 | */ | ||
139 | static inline int uv_apicid_to_nasid(int apicid) | ||
140 | { | ||
141 | return (UV_NASID(apicid >> UV_APIC_NASID_SHIFT)); | ||
142 | } | ||
143 | |||
144 | /* | ||
145 | * Access global MMRs using the low memory MMR32 space. This region supports | ||
146 | * faster MMR access but not all MMRs are accessible in this space. | ||
147 | */ | ||
148 | static inline unsigned long *uv_global_mmr32_address(int nasid, | ||
149 | unsigned long offset) | ||
150 | { | ||
151 | return __va(UV_GLOBAL_MMR32_BASE | | ||
152 | UV_GLOBAL_MMR32_NASID_BITS(nasid) | offset); | ||
153 | } | ||
154 | |||
155 | static inline void uv_write_global_mmr32(int nasid, unsigned long offset, | ||
156 | unsigned long val) | ||
157 | { | ||
158 | *uv_global_mmr32_address(nasid, offset) = val; | ||
159 | } | ||
160 | |||
161 | static inline unsigned long uv_read_global_mmr32(int nasid, | ||
162 | unsigned long offset) | ||
163 | { | ||
164 | return *uv_global_mmr32_address(nasid, offset); | ||
165 | } | ||
166 | |||
167 | /* | ||
168 | * Access Global MMR space using the MMR space located at the top of physical | ||
169 | * memory. | ||
170 | */ | ||
171 | static inline unsigned long *uv_global_mmr64_address(int nasid, | ||
172 | unsigned long offset) | ||
173 | { | ||
174 | return __va(UV_GLOBAL_MMR64_BASE | | ||
175 | UV_GLOBAL_MMR64_NASID_BITS(nasid) | offset); | ||
176 | } | ||
177 | |||
178 | static inline void uv_write_global_mmr64(int nasid, unsigned long offset, | ||
179 | unsigned long val) | ||
180 | { | ||
181 | *uv_global_mmr64_address(nasid, offset) = val; | ||
182 | } | ||
183 | |||
184 | static inline unsigned long uv_read_global_mmr64(int nasid, | ||
185 | unsigned long offset) | ||
186 | { | ||
187 | return *uv_global_mmr64_address(nasid, offset); | ||
188 | } | ||
189 | |||
190 | /* | ||
191 | * Access node local MMRs. Faster than using global space but only local MMRs | ||
192 | * are accessible. | ||
193 | */ | ||
194 | static inline unsigned long *uv_local_mmr_address(unsigned long offset) | ||
195 | { | ||
196 | return __va(UV_LOCAL_MMR_BASE | offset); | ||
197 | } | ||
198 | |||
199 | static inline unsigned long uv_read_local_mmr(unsigned long offset) | ||
200 | { | ||
201 | return *uv_local_mmr_address(offset); | ||
202 | } | ||
203 | |||
204 | static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) | ||
205 | { | ||
206 | *uv_local_mmr_address(offset) = val; | ||
207 | } | ||
208 | |||
209 | #endif /* __ASM_X86_UV_HUB__ */ | ||
210 | |||