diff options
| author | Ingo Molnar <mingo@elte.hu> | 2008-07-15 18:29:07 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-15 18:29:07 -0400 |
| commit | 82638844d9a8581bbf33201cc209a14876eca167 (patch) | |
| tree | 961d7f9360194421a71aa644a9d0c176a960ce49 /include/asm-x86/uv/uv_mmrs.h | |
| parent | 9982fbface82893e77d211fbabfbd229da6bdde6 (diff) | |
| parent | 63cf13b77ab785e87c867defa8545e6d4a989774 (diff) | |
Merge branch 'linus' into cpus4096
Conflicts:
arch/x86/xen/smp.c
kernel/sched_rt.c
net/iucv/iucv.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/uv/uv_mmrs.h')
| -rw-r--r-- | include/asm-x86/uv/uv_mmrs.h | 954 |
1 files changed, 938 insertions, 16 deletions
diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h index 3b69fe6b6376..151fd7fcb809 100644 --- a/include/asm-x86/uv/uv_mmrs.h +++ b/include/asm-x86/uv/uv_mmrs.h | |||
| @@ -11,17 +11,290 @@ | |||
| 11 | #ifndef __ASM_X86_UV_MMRS__ | 11 | #ifndef __ASM_X86_UV_MMRS__ |
| 12 | #define __ASM_X86_UV_MMRS__ | 12 | #define __ASM_X86_UV_MMRS__ |
| 13 | 13 | ||
| 14 | /* | 14 | #define UV_MMR_ENABLE (1UL << 63) |
| 15 | * AUTO GENERATED - Do not edit | 15 | |
| 16 | */ | 16 | /* ========================================================================= */ |
| 17 | /* UVH_BAU_DATA_CONFIG */ | ||
| 18 | /* ========================================================================= */ | ||
| 19 | #define UVH_BAU_DATA_CONFIG 0x61680UL | ||
| 20 | #define UVH_BAU_DATA_CONFIG_32 0x0438 | ||
| 21 | |||
| 22 | #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 | ||
| 23 | #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 24 | #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 | ||
| 25 | #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 26 | #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | ||
| 27 | #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 28 | #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 | ||
| 29 | #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 30 | #define UVH_BAU_DATA_CONFIG_P_SHFT 13 | ||
| 31 | #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | ||
| 32 | #define UVH_BAU_DATA_CONFIG_T_SHFT 15 | ||
| 33 | #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | ||
| 34 | #define UVH_BAU_DATA_CONFIG_M_SHFT 16 | ||
| 35 | #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | ||
| 36 | #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | ||
| 37 | #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 38 | |||
| 39 | union uvh_bau_data_config_u { | ||
| 40 | unsigned long v; | ||
| 41 | struct uvh_bau_data_config_s { | ||
| 42 | unsigned long vector_ : 8; /* RW */ | ||
| 43 | unsigned long dm : 3; /* RW */ | ||
| 44 | unsigned long destmode : 1; /* RW */ | ||
| 45 | unsigned long status : 1; /* RO */ | ||
| 46 | unsigned long p : 1; /* RO */ | ||
| 47 | unsigned long rsvd_14 : 1; /* */ | ||
| 48 | unsigned long t : 1; /* RO */ | ||
| 49 | unsigned long m : 1; /* RW */ | ||
| 50 | unsigned long rsvd_17_31: 15; /* */ | ||
| 51 | unsigned long apic_id : 32; /* RW */ | ||
| 52 | } s; | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* ========================================================================= */ | ||
| 56 | /* UVH_EVENT_OCCURRED0 */ | ||
| 57 | /* ========================================================================= */ | ||
| 58 | #define UVH_EVENT_OCCURRED0 0x70000UL | ||
| 59 | #define UVH_EVENT_OCCURRED0_32 0x005e8 | ||
| 60 | |||
| 61 | #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | ||
| 62 | #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | ||
| 63 | #define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 | ||
| 64 | #define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL | ||
| 65 | #define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 | ||
| 66 | #define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL | ||
| 67 | #define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3 | ||
| 68 | #define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL | ||
| 69 | #define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4 | ||
| 70 | #define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL | ||
| 71 | #define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5 | ||
| 72 | #define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL | ||
| 73 | #define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6 | ||
| 74 | #define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL | ||
| 75 | #define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 | ||
| 76 | #define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL | ||
| 77 | #define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 | ||
| 78 | #define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL | ||
| 79 | #define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 | ||
| 80 | #define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL | ||
| 81 | #define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 | ||
| 82 | #define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL | ||
| 83 | #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | ||
| 84 | #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | ||
| 85 | #define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 | ||
| 86 | #define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL | ||
| 87 | #define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 | ||
| 88 | #define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL | ||
| 89 | #define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 | ||
| 90 | #define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL | ||
| 91 | #define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 | ||
| 92 | #define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL | ||
| 93 | #define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 | ||
| 94 | #define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL | ||
| 95 | #define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 | ||
| 96 | #define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL | ||
| 97 | #define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 | ||
| 98 | #define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL | ||
| 99 | #define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 | ||
| 100 | #define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL | ||
| 101 | #define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 | ||
| 102 | #define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL | ||
| 103 | #define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 | ||
| 104 | #define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL | ||
| 105 | #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 | ||
| 106 | #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL | ||
| 107 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 | ||
| 108 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL | ||
| 109 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 | ||
| 110 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL | ||
| 111 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 | ||
| 112 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL | ||
| 113 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 | ||
| 114 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL | ||
| 115 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 | ||
| 116 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL | ||
| 117 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 | ||
| 118 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL | ||
| 119 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 | ||
| 120 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL | ||
| 121 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 | ||
| 122 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL | ||
| 123 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 | ||
| 124 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL | ||
| 125 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 | ||
| 126 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL | ||
| 127 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 | ||
| 128 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL | ||
| 129 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 | ||
| 130 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL | ||
| 131 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 | ||
| 132 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL | ||
| 133 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 | ||
| 134 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL | ||
| 135 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 | ||
| 136 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL | ||
| 137 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 | ||
| 138 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL | ||
| 139 | #define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 | ||
| 140 | #define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL | ||
| 141 | #define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 | ||
| 142 | #define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL | ||
| 143 | #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 | ||
| 144 | #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL | ||
| 145 | #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 | ||
| 146 | #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL | ||
| 147 | #define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43 | ||
| 148 | #define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL | ||
| 149 | #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 | ||
| 150 | #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL | ||
| 151 | #define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45 | ||
| 152 | #define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL | ||
| 153 | #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 | ||
| 154 | #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL | ||
| 155 | #define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 | ||
| 156 | #define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL | ||
| 157 | #define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 | ||
| 158 | #define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL | ||
| 159 | #define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 | ||
| 160 | #define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL | ||
| 161 | #define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 | ||
| 162 | #define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL | ||
| 163 | #define UVH_EVENT_OCCURRED0_RTC0_SHFT 51 | ||
| 164 | #define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL | ||
| 165 | #define UVH_EVENT_OCCURRED0_RTC1_SHFT 52 | ||
| 166 | #define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL | ||
| 167 | #define UVH_EVENT_OCCURRED0_RTC2_SHFT 53 | ||
| 168 | #define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL | ||
| 169 | #define UVH_EVENT_OCCURRED0_RTC3_SHFT 54 | ||
| 170 | #define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL | ||
| 171 | #define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55 | ||
| 172 | #define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL | ||
| 173 | #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 | ||
| 174 | #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL | ||
| 175 | union uvh_event_occurred0_u { | ||
| 176 | unsigned long v; | ||
| 177 | struct uvh_event_occurred0_s { | ||
| 178 | unsigned long lb_hcerr : 1; /* RW, W1C */ | ||
| 179 | unsigned long gr0_hcerr : 1; /* RW, W1C */ | ||
| 180 | unsigned long gr1_hcerr : 1; /* RW, W1C */ | ||
| 181 | unsigned long lh_hcerr : 1; /* RW, W1C */ | ||
| 182 | unsigned long rh_hcerr : 1; /* RW, W1C */ | ||
| 183 | unsigned long xn_hcerr : 1; /* RW, W1C */ | ||
| 184 | unsigned long si_hcerr : 1; /* RW, W1C */ | ||
| 185 | unsigned long lb_aoerr0 : 1; /* RW, W1C */ | ||
| 186 | unsigned long gr0_aoerr0 : 1; /* RW, W1C */ | ||
| 187 | unsigned long gr1_aoerr0 : 1; /* RW, W1C */ | ||
| 188 | unsigned long lh_aoerr0 : 1; /* RW, W1C */ | ||
| 189 | unsigned long rh_aoerr0 : 1; /* RW, W1C */ | ||
| 190 | unsigned long xn_aoerr0 : 1; /* RW, W1C */ | ||
| 191 | unsigned long si_aoerr0 : 1; /* RW, W1C */ | ||
| 192 | unsigned long lb_aoerr1 : 1; /* RW, W1C */ | ||
| 193 | unsigned long gr0_aoerr1 : 1; /* RW, W1C */ | ||
| 194 | unsigned long gr1_aoerr1 : 1; /* RW, W1C */ | ||
| 195 | unsigned long lh_aoerr1 : 1; /* RW, W1C */ | ||
| 196 | unsigned long rh_aoerr1 : 1; /* RW, W1C */ | ||
| 197 | unsigned long xn_aoerr1 : 1; /* RW, W1C */ | ||
| 198 | unsigned long si_aoerr1 : 1; /* RW, W1C */ | ||
| 199 | unsigned long rh_vpi_int : 1; /* RW, W1C */ | ||
| 200 | unsigned long system_shutdown_int : 1; /* RW, W1C */ | ||
| 201 | unsigned long lb_irq_int_0 : 1; /* RW, W1C */ | ||
| 202 | unsigned long lb_irq_int_1 : 1; /* RW, W1C */ | ||
| 203 | unsigned long lb_irq_int_2 : 1; /* RW, W1C */ | ||
| 204 | unsigned long lb_irq_int_3 : 1; /* RW, W1C */ | ||
| 205 | unsigned long lb_irq_int_4 : 1; /* RW, W1C */ | ||
| 206 | unsigned long lb_irq_int_5 : 1; /* RW, W1C */ | ||
| 207 | unsigned long lb_irq_int_6 : 1; /* RW, W1C */ | ||
| 208 | unsigned long lb_irq_int_7 : 1; /* RW, W1C */ | ||
| 209 | unsigned long lb_irq_int_8 : 1; /* RW, W1C */ | ||
| 210 | unsigned long lb_irq_int_9 : 1; /* RW, W1C */ | ||
| 211 | unsigned long lb_irq_int_10 : 1; /* RW, W1C */ | ||
| 212 | unsigned long lb_irq_int_11 : 1; /* RW, W1C */ | ||
| 213 | unsigned long lb_irq_int_12 : 1; /* RW, W1C */ | ||
| 214 | unsigned long lb_irq_int_13 : 1; /* RW, W1C */ | ||
| 215 | unsigned long lb_irq_int_14 : 1; /* RW, W1C */ | ||
| 216 | unsigned long lb_irq_int_15 : 1; /* RW, W1C */ | ||
| 217 | unsigned long l1_nmi_int : 1; /* RW, W1C */ | ||
| 218 | unsigned long stop_clock : 1; /* RW, W1C */ | ||
| 219 | unsigned long asic_to_l1 : 1; /* RW, W1C */ | ||
| 220 | unsigned long l1_to_asic : 1; /* RW, W1C */ | ||
| 221 | unsigned long ltc_int : 1; /* RW, W1C */ | ||
| 222 | unsigned long la_seq_trigger : 1; /* RW, W1C */ | ||
| 223 | unsigned long ipi_int : 1; /* RW, W1C */ | ||
| 224 | unsigned long extio_int0 : 1; /* RW, W1C */ | ||
| 225 | unsigned long extio_int1 : 1; /* RW, W1C */ | ||
| 226 | unsigned long extio_int2 : 1; /* RW, W1C */ | ||
| 227 | unsigned long extio_int3 : 1; /* RW, W1C */ | ||
| 228 | unsigned long profile_int : 1; /* RW, W1C */ | ||
| 229 | unsigned long rtc0 : 1; /* RW, W1C */ | ||
| 230 | unsigned long rtc1 : 1; /* RW, W1C */ | ||
| 231 | unsigned long rtc2 : 1; /* RW, W1C */ | ||
| 232 | unsigned long rtc3 : 1; /* RW, W1C */ | ||
| 233 | unsigned long bau_data : 1; /* RW, W1C */ | ||
| 234 | unsigned long power_management_req : 1; /* RW, W1C */ | ||
| 235 | unsigned long rsvd_57_63 : 7; /* */ | ||
| 236 | } s; | ||
| 237 | }; | ||
| 238 | |||
| 239 | /* ========================================================================= */ | ||
| 240 | /* UVH_EVENT_OCCURRED0_ALIAS */ | ||
| 241 | /* ========================================================================= */ | ||
| 242 | #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL | ||
| 243 | #define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 | ||
| 244 | |||
| 245 | /* ========================================================================= */ | ||
| 246 | /* UVH_INT_CMPB */ | ||
| 247 | /* ========================================================================= */ | ||
| 248 | #define UVH_INT_CMPB 0x22080UL | ||
| 249 | |||
| 250 | #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | ||
| 251 | #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | ||
| 252 | |||
| 253 | union uvh_int_cmpb_u { | ||
| 254 | unsigned long v; | ||
| 255 | struct uvh_int_cmpb_s { | ||
| 256 | unsigned long real_time_cmpb : 56; /* RW */ | ||
| 257 | unsigned long rsvd_56_63 : 8; /* */ | ||
| 258 | } s; | ||
| 259 | }; | ||
| 260 | |||
| 261 | /* ========================================================================= */ | ||
| 262 | /* UVH_INT_CMPC */ | ||
| 263 | /* ========================================================================= */ | ||
| 264 | #define UVH_INT_CMPC 0x22100UL | ||
| 265 | |||
| 266 | #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 | ||
| 267 | #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL | ||
| 268 | |||
| 269 | union uvh_int_cmpc_u { | ||
| 270 | unsigned long v; | ||
| 271 | struct uvh_int_cmpc_s { | ||
| 272 | unsigned long real_time_cmpc : 56; /* RW */ | ||
| 273 | unsigned long rsvd_56_63 : 8; /* */ | ||
| 274 | } s; | ||
| 275 | }; | ||
| 276 | |||
| 277 | /* ========================================================================= */ | ||
| 278 | /* UVH_INT_CMPD */ | ||
| 279 | /* ========================================================================= */ | ||
| 280 | #define UVH_INT_CMPD 0x22180UL | ||
| 17 | 281 | ||
| 18 | #define UV_MMR_ENABLE (1UL << 63) | 282 | #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 |
| 283 | #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL | ||
| 284 | |||
| 285 | union uvh_int_cmpd_u { | ||
| 286 | unsigned long v; | ||
| 287 | struct uvh_int_cmpd_s { | ||
| 288 | unsigned long real_time_cmpd : 56; /* RW */ | ||
| 289 | unsigned long rsvd_56_63 : 8; /* */ | ||
| 290 | } s; | ||
| 291 | }; | ||
| 19 | 292 | ||
| 20 | /* ========================================================================= */ | 293 | /* ========================================================================= */ |
| 21 | /* UVH_IPI_INT */ | 294 | /* UVH_IPI_INT */ |
| 22 | /* ========================================================================= */ | 295 | /* ========================================================================= */ |
| 23 | #define UVH_IPI_INT 0x60500UL | 296 | #define UVH_IPI_INT 0x60500UL |
| 24 | #define UVH_IPI_INT_32 0x0360 | 297 | #define UVH_IPI_INT_32 0x0348 |
| 25 | 298 | ||
| 26 | #define UVH_IPI_INT_VECTOR_SHFT 0 | 299 | #define UVH_IPI_INT_VECTOR_SHFT 0 |
| 27 | #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL | 300 | #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL |
| @@ -51,7 +324,7 @@ union uvh_ipi_int_u { | |||
| 51 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ | 324 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ |
| 52 | /* ========================================================================= */ | 325 | /* ========================================================================= */ |
| 53 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL | 326 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL |
| 54 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009f0 | 327 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0 |
| 55 | 328 | ||
| 56 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 | 329 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 |
| 57 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL | 330 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL |
| @@ -73,7 +346,7 @@ union uvh_lb_bau_intd_payload_queue_first_u { | |||
| 73 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ | 346 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ |
| 74 | /* ========================================================================= */ | 347 | /* ========================================================================= */ |
| 75 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL | 348 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL |
| 76 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009f8 | 349 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8 |
| 77 | 350 | ||
| 78 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 | 351 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 |
| 79 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL | 352 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL |
| @@ -91,7 +364,7 @@ union uvh_lb_bau_intd_payload_queue_last_u { | |||
| 91 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ | 364 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ |
| 92 | /* ========================================================================= */ | 365 | /* ========================================================================= */ |
| 93 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL | 366 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL |
| 94 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x00a00 | 367 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0 |
| 95 | 368 | ||
| 96 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 | 369 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 |
| 97 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL | 370 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL |
| @@ -109,6 +382,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u { | |||
| 109 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ | 382 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ |
| 110 | /* ========================================================================= */ | 383 | /* ========================================================================= */ |
| 111 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL | 384 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL |
| 385 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68 | ||
| 112 | 386 | ||
| 113 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | 387 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 |
| 114 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL | 388 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL |
| @@ -169,12 +443,13 @@ union uvh_lb_bau_intd_software_acknowledge_u { | |||
| 169 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ | 443 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ |
| 170 | /* ========================================================================= */ | 444 | /* ========================================================================= */ |
| 171 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL | 445 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL |
| 446 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70 | ||
| 172 | 447 | ||
| 173 | /* ========================================================================= */ | 448 | /* ========================================================================= */ |
| 174 | /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ | 449 | /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ |
| 175 | /* ========================================================================= */ | 450 | /* ========================================================================= */ |
| 176 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL | 451 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL |
| 177 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009d8 | 452 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8 |
| 178 | 453 | ||
| 179 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 | 454 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 |
| 180 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL | 455 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL |
| @@ -197,7 +472,7 @@ union uvh_lb_bau_sb_activation_control_u { | |||
| 197 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ | 472 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ |
| 198 | /* ========================================================================= */ | 473 | /* ========================================================================= */ |
| 199 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL | 474 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL |
| 200 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009e0 | 475 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0 |
| 201 | 476 | ||
| 202 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 | 477 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 |
| 203 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL | 478 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL |
| @@ -213,7 +488,7 @@ union uvh_lb_bau_sb_activation_status_0_u { | |||
| 213 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ | 488 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ |
| 214 | /* ========================================================================= */ | 489 | /* ========================================================================= */ |
| 215 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL | 490 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL |
| 216 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009e8 | 491 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8 |
| 217 | 492 | ||
| 218 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 | 493 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 |
| 219 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL | 494 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL |
| @@ -229,7 +504,7 @@ union uvh_lb_bau_sb_activation_status_1_u { | |||
| 229 | /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ | 504 | /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ |
| 230 | /* ========================================================================= */ | 505 | /* ========================================================================= */ |
| 231 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL | 506 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL |
| 232 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009d0 | 507 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0 |
| 233 | 508 | ||
| 234 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 | 509 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 |
| 235 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL | 510 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL |
| @@ -248,6 +523,334 @@ union uvh_lb_bau_sb_descriptor_base_u { | |||
| 248 | }; | 523 | }; |
| 249 | 524 | ||
| 250 | /* ========================================================================= */ | 525 | /* ========================================================================= */ |
| 526 | /* UVH_LB_MCAST_AOERR0_RPT_ENABLE */ | ||
| 527 | /* ========================================================================= */ | ||
| 528 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL | ||
| 529 | |||
| 530 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0 | ||
| 531 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL | ||
| 532 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1 | ||
| 533 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL | ||
| 534 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2 | ||
| 535 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL | ||
| 536 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3 | ||
| 537 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL | ||
| 538 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4 | ||
| 539 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL | ||
| 540 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5 | ||
| 541 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL | ||
| 542 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6 | ||
| 543 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL | ||
| 544 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7 | ||
| 545 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL | ||
| 546 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8 | ||
| 547 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL | ||
| 548 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9 | ||
| 549 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL | ||
| 550 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10 | ||
| 551 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL | ||
| 552 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11 | ||
| 553 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL | ||
| 554 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12 | ||
| 555 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL | ||
| 556 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13 | ||
| 557 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL | ||
| 558 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14 | ||
| 559 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL | ||
| 560 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15 | ||
| 561 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL | ||
| 562 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16 | ||
| 563 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL | ||
| 564 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17 | ||
| 565 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL | ||
| 566 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18 | ||
| 567 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL | ||
| 568 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19 | ||
| 569 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL | ||
| 570 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20 | ||
| 571 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL | ||
| 572 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21 | ||
| 573 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL | ||
| 574 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22 | ||
| 575 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL | ||
| 576 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23 | ||
| 577 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL | ||
| 578 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24 | ||
| 579 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL | ||
| 580 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25 | ||
| 581 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL | ||
| 582 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26 | ||
| 583 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL | ||
| 584 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27 | ||
| 585 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL | ||
| 586 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28 | ||
| 587 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL | ||
| 588 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29 | ||
| 589 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL | ||
| 590 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30 | ||
| 591 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL | ||
| 592 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31 | ||
| 593 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL | ||
| 594 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32 | ||
| 595 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL | ||
| 596 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33 | ||
| 597 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL | ||
| 598 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34 | ||
| 599 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL | ||
| 600 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35 | ||
| 601 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL | ||
| 602 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36 | ||
| 603 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL | ||
| 604 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37 | ||
| 605 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL | ||
| 606 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38 | ||
| 607 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL | ||
| 608 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39 | ||
| 609 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL | ||
| 610 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40 | ||
| 611 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL | ||
| 612 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41 | ||
| 613 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL | ||
| 614 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42 | ||
| 615 | #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL | ||
| 616 | |||
| 617 | union uvh_lb_mcast_aoerr0_rpt_enable_u { | ||
| 618 | unsigned long v; | ||
| 619 | struct uvh_lb_mcast_aoerr0_rpt_enable_s { | ||
| 620 | unsigned long mcast_obese_msg : 1; /* RW */ | ||
| 621 | unsigned long mcast_data_sb_err : 1; /* RW */ | ||
| 622 | unsigned long mcast_nack_buff_parity : 1; /* RW */ | ||
| 623 | unsigned long mcast_timeout : 1; /* RW */ | ||
| 624 | unsigned long mcast_inactive_reply : 1; /* RW */ | ||
| 625 | unsigned long mcast_upgrade_error : 1; /* RW */ | ||
| 626 | unsigned long mcast_reg_count_underflow : 1; /* RW */ | ||
| 627 | unsigned long mcast_rep_obese_msg : 1; /* RW */ | ||
| 628 | unsigned long ucache_req_runt_msg : 1; /* RW */ | ||
| 629 | unsigned long ucache_req_obese_msg : 1; /* RW */ | ||
| 630 | unsigned long ucache_req_data_sb_err : 1; /* RW */ | ||
| 631 | unsigned long ucache_rep_runt_msg : 1; /* RW */ | ||
| 632 | unsigned long ucache_rep_obese_msg : 1; /* RW */ | ||
| 633 | unsigned long ucache_rep_data_sb_err : 1; /* RW */ | ||
| 634 | unsigned long ucache_rep_command_err : 1; /* RW */ | ||
| 635 | unsigned long ucache_pend_timeout : 1; /* RW */ | ||
| 636 | unsigned long macc_req_runt_msg : 1; /* RW */ | ||
| 637 | unsigned long macc_req_obese_msg : 1; /* RW */ | ||
| 638 | unsigned long macc_req_data_sb_err : 1; /* RW */ | ||
| 639 | unsigned long macc_rep_runt_msg : 1; /* RW */ | ||
| 640 | unsigned long macc_rep_obese_msg : 1; /* RW */ | ||
| 641 | unsigned long macc_rep_data_sb_err : 1; /* RW */ | ||
| 642 | unsigned long macc_amo_timeout : 1; /* RW */ | ||
| 643 | unsigned long macc_put_timeout : 1; /* RW */ | ||
| 644 | unsigned long macc_spurious_event : 1; /* RW */ | ||
| 645 | unsigned long ioh_destination_table_parity : 1; /* RW */ | ||
| 646 | unsigned long get_had_error_reply : 1; /* RW */ | ||
| 647 | unsigned long get_timeout : 1; /* RW */ | ||
| 648 | unsigned long lock_manager_had_error_reply : 1; /* RW */ | ||
| 649 | unsigned long put_had_error_reply : 1; /* RW */ | ||
| 650 | unsigned long put_timeout : 1; /* RW */ | ||
| 651 | unsigned long sb_activation_overrun : 1; /* RW */ | ||
| 652 | unsigned long completed_gb_activation_had_error_reply : 1; /* RW */ | ||
| 653 | unsigned long completed_gb_activation_timeout : 1; /* RW */ | ||
| 654 | unsigned long descriptor_buffer_0_parity : 1; /* RW */ | ||
| 655 | unsigned long descriptor_buffer_1_parity : 1; /* RW */ | ||
| 656 | unsigned long socket_destination_table_parity : 1; /* RW */ | ||
| 657 | unsigned long bau_reply_payload_corruption : 1; /* RW */ | ||
| 658 | unsigned long io_port_destination_table_parity : 1; /* RW */ | ||
| 659 | unsigned long intd_soft_ack_timeout : 1; /* RW */ | ||
| 660 | unsigned long int_rep_obese_msg : 1; /* RW */ | ||
| 661 | unsigned long int_rep_command_err : 1; /* RW */ | ||
| 662 | unsigned long int_timeout : 1; /* RW */ | ||
| 663 | unsigned long rsvd_43_63 : 21; /* */ | ||
| 664 | } s; | ||
| 665 | }; | ||
| 666 | |||
| 667 | /* ========================================================================= */ | ||
| 668 | /* UVH_LOCAL_INT0_CONFIG */ | ||
| 669 | /* ========================================================================= */ | ||
| 670 | #define UVH_LOCAL_INT0_CONFIG 0x61000UL | ||
| 671 | |||
| 672 | #define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0 | ||
| 673 | #define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 674 | #define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8 | ||
| 675 | #define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 676 | #define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11 | ||
| 677 | #define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 678 | #define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12 | ||
| 679 | #define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 680 | #define UVH_LOCAL_INT0_CONFIG_P_SHFT 13 | ||
| 681 | #define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL | ||
| 682 | #define UVH_LOCAL_INT0_CONFIG_T_SHFT 15 | ||
| 683 | #define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL | ||
| 684 | #define UVH_LOCAL_INT0_CONFIG_M_SHFT 16 | ||
| 685 | #define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL | ||
| 686 | #define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32 | ||
| 687 | #define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 688 | |||
| 689 | union uvh_local_int0_config_u { | ||
| 690 | unsigned long v; | ||
| 691 | struct uvh_local_int0_config_s { | ||
| 692 | unsigned long vector_ : 8; /* RW */ | ||
| 693 | unsigned long dm : 3; /* RW */ | ||
| 694 | unsigned long destmode : 1; /* RW */ | ||
| 695 | unsigned long status : 1; /* RO */ | ||
| 696 | unsigned long p : 1; /* RO */ | ||
| 697 | unsigned long rsvd_14 : 1; /* */ | ||
| 698 | unsigned long t : 1; /* RO */ | ||
| 699 | unsigned long m : 1; /* RW */ | ||
| 700 | unsigned long rsvd_17_31: 15; /* */ | ||
| 701 | unsigned long apic_id : 32; /* RW */ | ||
| 702 | } s; | ||
| 703 | }; | ||
| 704 | |||
| 705 | /* ========================================================================= */ | ||
| 706 | /* UVH_LOCAL_INT0_ENABLE */ | ||
| 707 | /* ========================================================================= */ | ||
| 708 | #define UVH_LOCAL_INT0_ENABLE 0x65000UL | ||
| 709 | |||
| 710 | #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0 | ||
| 711 | #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL | ||
| 712 | #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1 | ||
| 713 | #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL | ||
| 714 | #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2 | ||
| 715 | #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL | ||
| 716 | #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3 | ||
| 717 | #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL | ||
| 718 | #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4 | ||
| 719 | #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL | ||
| 720 | #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5 | ||
| 721 | #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL | ||
| 722 | #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6 | ||
| 723 | #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL | ||
| 724 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7 | ||
| 725 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL | ||
| 726 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8 | ||
| 727 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL | ||
| 728 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9 | ||
| 729 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL | ||
| 730 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10 | ||
| 731 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL | ||
| 732 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11 | ||
| 733 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL | ||
| 734 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12 | ||
| 735 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL | ||
| 736 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13 | ||
| 737 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL | ||
| 738 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14 | ||
| 739 | #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL | ||
| 740 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15 | ||
| 741 | #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL | ||
| 742 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16 | ||
| 743 | #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL | ||
| 744 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17 | ||
| 745 | #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL | ||
| 746 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18 | ||
| 747 | #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL | ||
| 748 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19 | ||
| 749 | #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL | ||
| 750 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20 | ||
| 751 | #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL | ||
| 752 | #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21 | ||
| 753 | #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL | ||
| 754 | #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22 | ||
| 755 | #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL | ||
| 756 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23 | ||
| 757 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL | ||
| 758 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24 | ||
| 759 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL | ||
| 760 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25 | ||
| 761 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL | ||
| 762 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26 | ||
| 763 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL | ||
| 764 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27 | ||
| 765 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL | ||
| 766 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28 | ||
| 767 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL | ||
| 768 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29 | ||
| 769 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL | ||
| 770 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30 | ||
| 771 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL | ||
| 772 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31 | ||
| 773 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL | ||
| 774 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32 | ||
| 775 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL | ||
| 776 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33 | ||
| 777 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL | ||
| 778 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34 | ||
| 779 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL | ||
| 780 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35 | ||
| 781 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL | ||
| 782 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36 | ||
| 783 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL | ||
| 784 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37 | ||
| 785 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL | ||
| 786 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38 | ||
| 787 | #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL | ||
| 788 | #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39 | ||
| 789 | #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL | ||
| 790 | #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40 | ||
| 791 | #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL | ||
| 792 | #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41 | ||
| 793 | #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL | ||
| 794 | #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42 | ||
| 795 | #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL | ||
| 796 | #define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43 | ||
| 797 | #define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL | ||
| 798 | #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44 | ||
| 799 | #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL | ||
| 800 | |||
| 801 | union uvh_local_int0_enable_u { | ||
| 802 | unsigned long v; | ||
| 803 | struct uvh_local_int0_enable_s { | ||
| 804 | unsigned long lb_hcerr : 1; /* RW */ | ||
| 805 | unsigned long gr0_hcerr : 1; /* RW */ | ||
| 806 | unsigned long gr1_hcerr : 1; /* RW */ | ||
| 807 | unsigned long lh_hcerr : 1; /* RW */ | ||
| 808 | unsigned long rh_hcerr : 1; /* RW */ | ||
| 809 | unsigned long xn_hcerr : 1; /* RW */ | ||
| 810 | unsigned long si_hcerr : 1; /* RW */ | ||
| 811 | unsigned long lb_aoerr0 : 1; /* RW */ | ||
| 812 | unsigned long gr0_aoerr0 : 1; /* RW */ | ||
| 813 | unsigned long gr1_aoerr0 : 1; /* RW */ | ||
| 814 | unsigned long lh_aoerr0 : 1; /* RW */ | ||
| 815 | unsigned long rh_aoerr0 : 1; /* RW */ | ||
| 816 | unsigned long xn_aoerr0 : 1; /* RW */ | ||
| 817 | unsigned long si_aoerr0 : 1; /* RW */ | ||
| 818 | unsigned long lb_aoerr1 : 1; /* RW */ | ||
| 819 | unsigned long gr0_aoerr1 : 1; /* RW */ | ||
| 820 | unsigned long gr1_aoerr1 : 1; /* RW */ | ||
| 821 | unsigned long lh_aoerr1 : 1; /* RW */ | ||
| 822 | unsigned long rh_aoerr1 : 1; /* RW */ | ||
| 823 | unsigned long xn_aoerr1 : 1; /* RW */ | ||
| 824 | unsigned long si_aoerr1 : 1; /* RW */ | ||
| 825 | unsigned long rh_vpi_int : 1; /* RW */ | ||
| 826 | unsigned long system_shutdown_int : 1; /* RW */ | ||
| 827 | unsigned long lb_irq_int_0 : 1; /* RW */ | ||
| 828 | unsigned long lb_irq_int_1 : 1; /* RW */ | ||
| 829 | unsigned long lb_irq_int_2 : 1; /* RW */ | ||
| 830 | unsigned long lb_irq_int_3 : 1; /* RW */ | ||
| 831 | unsigned long lb_irq_int_4 : 1; /* RW */ | ||
| 832 | unsigned long lb_irq_int_5 : 1; /* RW */ | ||
| 833 | unsigned long lb_irq_int_6 : 1; /* RW */ | ||
| 834 | unsigned long lb_irq_int_7 : 1; /* RW */ | ||
| 835 | unsigned long lb_irq_int_8 : 1; /* RW */ | ||
| 836 | unsigned long lb_irq_int_9 : 1; /* RW */ | ||
| 837 | unsigned long lb_irq_int_10 : 1; /* RW */ | ||
| 838 | unsigned long lb_irq_int_11 : 1; /* RW */ | ||
| 839 | unsigned long lb_irq_int_12 : 1; /* RW */ | ||
| 840 | unsigned long lb_irq_int_13 : 1; /* RW */ | ||
| 841 | unsigned long lb_irq_int_14 : 1; /* RW */ | ||
| 842 | unsigned long lb_irq_int_15 : 1; /* RW */ | ||
| 843 | unsigned long l1_nmi_int : 1; /* RW */ | ||
| 844 | unsigned long stop_clock : 1; /* RW */ | ||
| 845 | unsigned long asic_to_l1 : 1; /* RW */ | ||
| 846 | unsigned long l1_to_asic : 1; /* RW */ | ||
| 847 | unsigned long ltc_int : 1; /* RW */ | ||
| 848 | unsigned long la_seq_trigger : 1; /* RW */ | ||
| 849 | unsigned long rsvd_45_63 : 19; /* */ | ||
| 850 | } s; | ||
| 851 | }; | ||
| 852 | |||
| 853 | /* ========================================================================= */ | ||
| 251 | /* UVH_NODE_ID */ | 854 | /* UVH_NODE_ID */ |
| 252 | /* ========================================================================= */ | 855 | /* ========================================================================= */ |
| 253 | #define UVH_NODE_ID 0x0UL | 856 | #define UVH_NODE_ID 0x0UL |
| @@ -284,14 +887,101 @@ union uvh_node_id_u { | |||
| 284 | }; | 887 | }; |
| 285 | 888 | ||
| 286 | /* ========================================================================= */ | 889 | /* ========================================================================= */ |
| 890 | /* UVH_NODE_PRESENT_TABLE */ | ||
| 891 | /* ========================================================================= */ | ||
| 892 | #define UVH_NODE_PRESENT_TABLE 0x1400UL | ||
| 893 | #define UVH_NODE_PRESENT_TABLE_DEPTH 16 | ||
| 894 | |||
| 895 | #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 | ||
| 896 | #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | ||
| 897 | |||
| 898 | union uvh_node_present_table_u { | ||
| 899 | unsigned long v; | ||
| 900 | struct uvh_node_present_table_s { | ||
| 901 | unsigned long nodes : 64; /* RW */ | ||
| 902 | } s; | ||
| 903 | }; | ||
| 904 | |||
| 905 | /* ========================================================================= */ | ||
| 906 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ | ||
| 907 | /* ========================================================================= */ | ||
| 908 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | ||
| 909 | |||
| 910 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | ||
| 911 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 912 | |||
| 913 | union uvh_rh_gam_alias210_redirect_config_0_mmr_u { | ||
| 914 | unsigned long v; | ||
| 915 | struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { | ||
| 916 | unsigned long rsvd_0_23 : 24; /* */ | ||
| 917 | unsigned long dest_base : 22; /* RW */ | ||
| 918 | unsigned long rsvd_46_63: 18; /* */ | ||
| 919 | } s; | ||
| 920 | }; | ||
| 921 | |||
| 922 | /* ========================================================================= */ | ||
| 923 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ | ||
| 924 | /* ========================================================================= */ | ||
| 925 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | ||
| 926 | |||
| 927 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | ||
| 928 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 929 | |||
| 930 | union uvh_rh_gam_alias210_redirect_config_1_mmr_u { | ||
| 931 | unsigned long v; | ||
| 932 | struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { | ||
| 933 | unsigned long rsvd_0_23 : 24; /* */ | ||
| 934 | unsigned long dest_base : 22; /* RW */ | ||
| 935 | unsigned long rsvd_46_63: 18; /* */ | ||
| 936 | } s; | ||
| 937 | }; | ||
| 938 | |||
| 939 | /* ========================================================================= */ | ||
| 940 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ | ||
| 941 | /* ========================================================================= */ | ||
| 942 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | ||
| 943 | |||
| 944 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | ||
| 945 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | ||
| 946 | |||
| 947 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | ||
| 948 | unsigned long v; | ||
| 949 | struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { | ||
| 950 | unsigned long rsvd_0_23 : 24; /* */ | ||
| 951 | unsigned long dest_base : 22; /* RW */ | ||
| 952 | unsigned long rsvd_46_63: 18; /* */ | ||
| 953 | } s; | ||
| 954 | }; | ||
| 955 | |||
| 956 | /* ========================================================================= */ | ||
| 957 | /* UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR */ | ||
| 958 | /* ========================================================================= */ | ||
| 959 | #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL | ||
| 960 | |||
| 961 | #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | ||
| 962 | #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | ||
| 963 | #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 964 | #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 965 | |||
| 966 | union uvh_rh_gam_cfg_overlay_config_mmr_u { | ||
| 967 | unsigned long v; | ||
| 968 | struct uvh_rh_gam_cfg_overlay_config_mmr_s { | ||
| 969 | unsigned long rsvd_0_25: 26; /* */ | ||
| 970 | unsigned long base : 20; /* RW */ | ||
| 971 | unsigned long rsvd_46_62: 17; /* */ | ||
| 972 | unsigned long enable : 1; /* RW */ | ||
| 973 | } s; | ||
| 974 | }; | ||
| 975 | |||
| 976 | /* ========================================================================= */ | ||
| 287 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ | 977 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ |
| 288 | /* ========================================================================= */ | 978 | /* ========================================================================= */ |
| 289 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | 979 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL |
| 290 | 980 | ||
| 291 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | 981 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 |
| 292 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | 982 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL |
| 293 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46 | 983 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 |
| 294 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL | 984 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL |
| 295 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | 985 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 |
| 296 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | 986 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL |
| 297 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | 987 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 |
| @@ -302,8 +992,9 @@ union uvh_rh_gam_gru_overlay_config_mmr_u { | |||
| 302 | struct uvh_rh_gam_gru_overlay_config_mmr_s { | 992 | struct uvh_rh_gam_gru_overlay_config_mmr_s { |
| 303 | unsigned long rsvd_0_27: 28; /* */ | 993 | unsigned long rsvd_0_27: 28; /* */ |
| 304 | unsigned long base : 18; /* RW */ | 994 | unsigned long base : 18; /* RW */ |
| 995 | unsigned long rsvd_46_47: 2; /* */ | ||
| 305 | unsigned long gr4 : 1; /* RW */ | 996 | unsigned long gr4 : 1; /* RW */ |
| 306 | unsigned long rsvd_47_51: 5; /* */ | 997 | unsigned long rsvd_49_51: 3; /* */ |
| 307 | unsigned long n_gru : 4; /* RW */ | 998 | unsigned long n_gru : 4; /* RW */ |
| 308 | unsigned long rsvd_56_62: 7; /* */ | 999 | unsigned long rsvd_56_62: 7; /* */ |
| 309 | unsigned long enable : 1; /* RW */ | 1000 | unsigned long enable : 1; /* RW */ |
| @@ -311,6 +1002,32 @@ union uvh_rh_gam_gru_overlay_config_mmr_u { | |||
| 311 | }; | 1002 | }; |
| 312 | 1003 | ||
| 313 | /* ========================================================================= */ | 1004 | /* ========================================================================= */ |
| 1005 | /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ | ||
| 1006 | /* ========================================================================= */ | ||
| 1007 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL | ||
| 1008 | |||
| 1009 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 | ||
| 1010 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL | ||
| 1011 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 | ||
| 1012 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL | ||
| 1013 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 | ||
| 1014 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL | ||
| 1015 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | ||
| 1016 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | ||
| 1017 | |||
| 1018 | union uvh_rh_gam_mmioh_overlay_config_mmr_u { | ||
| 1019 | unsigned long v; | ||
| 1020 | struct uvh_rh_gam_mmioh_overlay_config_mmr_s { | ||
| 1021 | unsigned long rsvd_0_29: 30; /* */ | ||
| 1022 | unsigned long base : 16; /* RW */ | ||
| 1023 | unsigned long m_io : 6; /* RW */ | ||
| 1024 | unsigned long n_io : 4; /* RW */ | ||
| 1025 | unsigned long rsvd_56_62: 7; /* */ | ||
| 1026 | unsigned long enable : 1; /* RW */ | ||
| 1027 | } s; | ||
| 1028 | }; | ||
| 1029 | |||
| 1030 | /* ========================================================================= */ | ||
| 314 | /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ | 1031 | /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ |
| 315 | /* ========================================================================= */ | 1032 | /* ========================================================================= */ |
| 316 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL | 1033 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL |
| @@ -336,7 +1053,7 @@ union uvh_rh_gam_mmr_overlay_config_mmr_u { | |||
| 336 | /* ========================================================================= */ | 1053 | /* ========================================================================= */ |
| 337 | /* UVH_RTC */ | 1054 | /* UVH_RTC */ |
| 338 | /* ========================================================================= */ | 1055 | /* ========================================================================= */ |
| 339 | #define UVH_RTC 0x28000UL | 1056 | #define UVH_RTC 0x340000UL |
| 340 | 1057 | ||
| 341 | #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 | 1058 | #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 |
| 342 | #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | 1059 | #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL |
| @@ -350,6 +1067,139 @@ union uvh_rtc_u { | |||
| 350 | }; | 1067 | }; |
| 351 | 1068 | ||
| 352 | /* ========================================================================= */ | 1069 | /* ========================================================================= */ |
| 1070 | /* UVH_RTC1_INT_CONFIG */ | ||
| 1071 | /* ========================================================================= */ | ||
| 1072 | #define UVH_RTC1_INT_CONFIG 0x615c0UL | ||
| 1073 | |||
| 1074 | #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 | ||
| 1075 | #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1076 | #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 | ||
| 1077 | #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1078 | #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | ||
| 1079 | #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1080 | #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 | ||
| 1081 | #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1082 | #define UVH_RTC1_INT_CONFIG_P_SHFT 13 | ||
| 1083 | #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1084 | #define UVH_RTC1_INT_CONFIG_T_SHFT 15 | ||
| 1085 | #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1086 | #define UVH_RTC1_INT_CONFIG_M_SHFT 16 | ||
| 1087 | #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1088 | #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | ||
| 1089 | #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1090 | |||
| 1091 | union uvh_rtc1_int_config_u { | ||
| 1092 | unsigned long v; | ||
| 1093 | struct uvh_rtc1_int_config_s { | ||
| 1094 | unsigned long vector_ : 8; /* RW */ | ||
| 1095 | unsigned long dm : 3; /* RW */ | ||
| 1096 | unsigned long destmode : 1; /* RW */ | ||
| 1097 | unsigned long status : 1; /* RO */ | ||
| 1098 | unsigned long p : 1; /* RO */ | ||
| 1099 | unsigned long rsvd_14 : 1; /* */ | ||
| 1100 | unsigned long t : 1; /* RO */ | ||
| 1101 | unsigned long m : 1; /* RW */ | ||
| 1102 | unsigned long rsvd_17_31: 15; /* */ | ||
| 1103 | unsigned long apic_id : 32; /* RW */ | ||
| 1104 | } s; | ||
| 1105 | }; | ||
| 1106 | |||
| 1107 | /* ========================================================================= */ | ||
| 1108 | /* UVH_RTC2_INT_CONFIG */ | ||
| 1109 | /* ========================================================================= */ | ||
| 1110 | #define UVH_RTC2_INT_CONFIG 0x61600UL | ||
| 1111 | |||
| 1112 | #define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0 | ||
| 1113 | #define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1114 | #define UVH_RTC2_INT_CONFIG_DM_SHFT 8 | ||
| 1115 | #define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1116 | #define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11 | ||
| 1117 | #define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1118 | #define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12 | ||
| 1119 | #define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1120 | #define UVH_RTC2_INT_CONFIG_P_SHFT 13 | ||
| 1121 | #define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1122 | #define UVH_RTC2_INT_CONFIG_T_SHFT 15 | ||
| 1123 | #define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1124 | #define UVH_RTC2_INT_CONFIG_M_SHFT 16 | ||
| 1125 | #define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1126 | #define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32 | ||
| 1127 | #define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1128 | |||
| 1129 | union uvh_rtc2_int_config_u { | ||
| 1130 | unsigned long v; | ||
| 1131 | struct uvh_rtc2_int_config_s { | ||
| 1132 | unsigned long vector_ : 8; /* RW */ | ||
| 1133 | unsigned long dm : 3; /* RW */ | ||
| 1134 | unsigned long destmode : 1; /* RW */ | ||
| 1135 | unsigned long status : 1; /* RO */ | ||
| 1136 | unsigned long p : 1; /* RO */ | ||
| 1137 | unsigned long rsvd_14 : 1; /* */ | ||
| 1138 | unsigned long t : 1; /* RO */ | ||
| 1139 | unsigned long m : 1; /* RW */ | ||
| 1140 | unsigned long rsvd_17_31: 15; /* */ | ||
| 1141 | unsigned long apic_id : 32; /* RW */ | ||
| 1142 | } s; | ||
| 1143 | }; | ||
| 1144 | |||
| 1145 | /* ========================================================================= */ | ||
| 1146 | /* UVH_RTC3_INT_CONFIG */ | ||
| 1147 | /* ========================================================================= */ | ||
| 1148 | #define UVH_RTC3_INT_CONFIG 0x61640UL | ||
| 1149 | |||
| 1150 | #define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0 | ||
| 1151 | #define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | ||
| 1152 | #define UVH_RTC3_INT_CONFIG_DM_SHFT 8 | ||
| 1153 | #define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL | ||
| 1154 | #define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11 | ||
| 1155 | #define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | ||
| 1156 | #define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12 | ||
| 1157 | #define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | ||
| 1158 | #define UVH_RTC3_INT_CONFIG_P_SHFT 13 | ||
| 1159 | #define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL | ||
| 1160 | #define UVH_RTC3_INT_CONFIG_T_SHFT 15 | ||
| 1161 | #define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL | ||
| 1162 | #define UVH_RTC3_INT_CONFIG_M_SHFT 16 | ||
| 1163 | #define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL | ||
| 1164 | #define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32 | ||
| 1165 | #define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | ||
| 1166 | |||
| 1167 | union uvh_rtc3_int_config_u { | ||
| 1168 | unsigned long v; | ||
| 1169 | struct uvh_rtc3_int_config_s { | ||
| 1170 | unsigned long vector_ : 8; /* RW */ | ||
| 1171 | unsigned long dm : 3; /* RW */ | ||
| 1172 | unsigned long destmode : 1; /* RW */ | ||
| 1173 | unsigned long status : 1; /* RO */ | ||
| 1174 | unsigned long p : 1; /* RO */ | ||
| 1175 | unsigned long rsvd_14 : 1; /* */ | ||
| 1176 | unsigned long t : 1; /* RO */ | ||
| 1177 | unsigned long m : 1; /* RW */ | ||
| 1178 | unsigned long rsvd_17_31: 15; /* */ | ||
| 1179 | unsigned long apic_id : 32; /* RW */ | ||
| 1180 | } s; | ||
| 1181 | }; | ||
| 1182 | |||
| 1183 | /* ========================================================================= */ | ||
| 1184 | /* UVH_RTC_INC_RATIO */ | ||
| 1185 | /* ========================================================================= */ | ||
| 1186 | #define UVH_RTC_INC_RATIO 0x350000UL | ||
| 1187 | |||
| 1188 | #define UVH_RTC_INC_RATIO_FRACTION_SHFT 0 | ||
| 1189 | #define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL | ||
| 1190 | #define UVH_RTC_INC_RATIO_RATIO_SHFT 20 | ||
| 1191 | #define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL | ||
| 1192 | |||
| 1193 | union uvh_rtc_inc_ratio_u { | ||
| 1194 | unsigned long v; | ||
| 1195 | struct uvh_rtc_inc_ratio_s { | ||
| 1196 | unsigned long fraction : 20; /* RW */ | ||
| 1197 | unsigned long ratio : 3; /* RW */ | ||
| 1198 | unsigned long rsvd_23_63: 41; /* */ | ||
| 1199 | } s; | ||
| 1200 | }; | ||
| 1201 | |||
| 1202 | /* ========================================================================= */ | ||
| 353 | /* UVH_SI_ADDR_MAP_CONFIG */ | 1203 | /* UVH_SI_ADDR_MAP_CONFIG */ |
| 354 | /* ========================================================================= */ | 1204 | /* ========================================================================= */ |
| 355 | #define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL | 1205 | #define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL |
| @@ -369,5 +1219,77 @@ union uvh_si_addr_map_config_u { | |||
| 369 | } s; | 1219 | } s; |
| 370 | }; | 1220 | }; |
| 371 | 1221 | ||
| 1222 | /* ========================================================================= */ | ||
| 1223 | /* UVH_SI_ALIAS0_OVERLAY_CONFIG */ | ||
| 1224 | /* ========================================================================= */ | ||
| 1225 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL | ||
| 1226 | |||
| 1227 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24 | ||
| 1228 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | ||
| 1229 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | ||
| 1230 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | ||
| 1231 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63 | ||
| 1232 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | ||
| 1233 | |||
| 1234 | union uvh_si_alias0_overlay_config_u { | ||
| 1235 | unsigned long v; | ||
| 1236 | struct uvh_si_alias0_overlay_config_s { | ||
| 1237 | unsigned long rsvd_0_23: 24; /* */ | ||
| 1238 | unsigned long base : 8; /* RW */ | ||
| 1239 | unsigned long rsvd_32_47: 16; /* */ | ||
| 1240 | unsigned long m_alias : 5; /* RW */ | ||
| 1241 | unsigned long rsvd_53_62: 10; /* */ | ||
| 1242 | unsigned long enable : 1; /* RW */ | ||
| 1243 | } s; | ||
| 1244 | }; | ||
| 1245 | |||
| 1246 | /* ========================================================================= */ | ||
| 1247 | /* UVH_SI_ALIAS1_OVERLAY_CONFIG */ | ||
| 1248 | /* ========================================================================= */ | ||
| 1249 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL | ||
| 1250 | |||
| 1251 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24 | ||
| 1252 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | ||
| 1253 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | ||
| 1254 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | ||
| 1255 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63 | ||
| 1256 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | ||
| 1257 | |||
| 1258 | union uvh_si_alias1_overlay_config_u { | ||
| 1259 | unsigned long v; | ||
| 1260 | struct uvh_si_alias1_overlay_config_s { | ||
| 1261 | unsigned long rsvd_0_23: 24; /* */ | ||
| 1262 | unsigned long base : 8; /* RW */ | ||
| 1263 | unsigned long rsvd_32_47: 16; /* */ | ||
| 1264 | unsigned long m_alias : 5; /* RW */ | ||
| 1265 | unsigned long rsvd_53_62: 10; /* */ | ||
| 1266 | unsigned long enable : 1; /* RW */ | ||
| 1267 | } s; | ||
| 1268 | }; | ||
| 1269 | |||
| 1270 | /* ========================================================================= */ | ||
| 1271 | /* UVH_SI_ALIAS2_OVERLAY_CONFIG */ | ||
| 1272 | /* ========================================================================= */ | ||
| 1273 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL | ||
| 1274 | |||
| 1275 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24 | ||
| 1276 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | ||
| 1277 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | ||
| 1278 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | ||
| 1279 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63 | ||
| 1280 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | ||
| 1281 | |||
| 1282 | union uvh_si_alias2_overlay_config_u { | ||
| 1283 | unsigned long v; | ||
| 1284 | struct uvh_si_alias2_overlay_config_s { | ||
| 1285 | unsigned long rsvd_0_23: 24; /* */ | ||
| 1286 | unsigned long base : 8; /* RW */ | ||
| 1287 | unsigned long rsvd_32_47: 16; /* */ | ||
| 1288 | unsigned long m_alias : 5; /* RW */ | ||
| 1289 | unsigned long rsvd_53_62: 10; /* */ | ||
| 1290 | unsigned long enable : 1; /* RW */ | ||
| 1291 | } s; | ||
| 1292 | }; | ||
| 1293 | |||
| 372 | 1294 | ||
| 373 | #endif /* __ASM_X86_UV_MMRS__ */ | 1295 | #endif /* __ASM_X86_UV_MMRS__ */ |