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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-08-19 09:55:09 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:42 -0400
commitd10e025f0e4ba4b96d7b5786d232ac5b0b232b11 (patch)
treea417a55071b4b7edc22b7c5bb1a2352e7b5986d9 /include/asm-x86/ucontext.h
parent860e546c19d88c21819c7f0861c505debd2d6eed (diff)
MIPS: TXx9: Cache fixup
TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options to control them. This is useful to debug some cache-related issues, such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-x86/ucontext.h')
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