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authorJoe Perches <joe@perches.com>2008-03-23 04:03:20 -0400
committerIngo Molnar <mingo@elte.hu>2008-04-17 11:41:27 -0400
commit0f4fc8c1dca86b519fed50be0962c8def8d3d446 (patch)
treea4467ef1043ef18c91f887d84d78b83ae0e8f7a7 /include/asm-x86/rio.h
parentc6fd5d49ec578e1078331b81ca09008fb361a8ba (diff)
include/asm-x86/rio.h: checkpatch cleanups - formatting only
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/rio.h')
-rw-r--r--include/asm-x86/rio.h76
1 files changed, 38 insertions, 38 deletions
diff --git a/include/asm-x86/rio.h b/include/asm-x86/rio.h
index 97cdcc9887ba..3451c576e6af 100644
--- a/include/asm-x86/rio.h
+++ b/include/asm-x86/rio.h
@@ -11,53 +11,53 @@
11#define RIO_TABLE_VERSION 3 11#define RIO_TABLE_VERSION 3
12 12
13struct rio_table_hdr { 13struct rio_table_hdr {
14 u8 version; /* Version number of this data structure */ 14 u8 version; /* Version number of this data structure */
15 u8 num_scal_dev; /* # of Scalability devices */ 15 u8 num_scal_dev; /* # of Scalability devices */
16 u8 num_rio_dev; /* # of RIO I/O devices */ 16 u8 num_rio_dev; /* # of RIO I/O devices */
17} __attribute__((packed)); 17} __attribute__((packed));
18 18
19struct scal_detail { 19struct scal_detail {
20 u8 node_id; /* Scalability Node ID */ 20 u8 node_id; /* Scalability Node ID */
21 u32 CBAR; /* Address of 1MB register space */ 21 u32 CBAR; /* Address of 1MB register space */
22 u8 port0node; /* Node ID port connected to: 0xFF=None */ 22 u8 port0node; /* Node ID port connected to: 0xFF=None */
23 u8 port0port; /* Port num port connected to: 0,1,2, or */ 23 u8 port0port; /* Port num port connected to: 0,1,2, or */
24 /* 0xFF=None */ 24 /* 0xFF=None */
25 u8 port1node; /* Node ID port connected to: 0xFF = None */ 25 u8 port1node; /* Node ID port connected to: 0xFF = None */
26 u8 port1port; /* Port num port connected to: 0,1,2, or */ 26 u8 port1port; /* Port num port connected to: 0,1,2, or */
27 /* 0xFF=None */ 27 /* 0xFF=None */
28 u8 port2node; /* Node ID port connected to: 0xFF = None */ 28 u8 port2node; /* Node ID port connected to: 0xFF = None */
29 u8 port2port; /* Port num port connected to: 0,1,2, or */ 29 u8 port2port; /* Port num port connected to: 0,1,2, or */
30 /* 0xFF=None */ 30 /* 0xFF=None */
31 u8 chassis_num; /* 1 based Chassis number (1 = boot node) */ 31 u8 chassis_num; /* 1 based Chassis number (1 = boot node) */
32} __attribute__((packed)); 32} __attribute__((packed));
33 33
34struct rio_detail { 34struct rio_detail {
35 u8 node_id; /* RIO Node ID */ 35 u8 node_id; /* RIO Node ID */
36 u32 BBAR; /* Address of 1MB register space */ 36 u32 BBAR; /* Address of 1MB register space */
37 u8 type; /* Type of device */ 37 u8 type; /* Type of device */
38 u8 owner_id; /* Node ID of Hurricane that owns this */ 38 u8 owner_id; /* Node ID of Hurricane that owns this */
39 /* node */ 39 /* node */
40 u8 port0node; /* Node ID port connected to: 0xFF=None */ 40 u8 port0node; /* Node ID port connected to: 0xFF=None */
41 u8 port0port; /* Port num port connected to: 0,1,2, or */ 41 u8 port0port; /* Port num port connected to: 0,1,2, or */
42 /* 0xFF=None */ 42 /* 0xFF=None */
43 u8 port1node; /* Node ID port connected to: 0xFF=None */ 43 u8 port1node; /* Node ID port connected to: 0xFF=None */
44 u8 port1port; /* Port num port connected to: 0,1,2, or */ 44 u8 port1port; /* Port num port connected to: 0,1,2, or */
45 /* 0xFF=None */ 45 /* 0xFF=None */
46 u8 first_slot; /* Lowest slot number below this Calgary */ 46 u8 first_slot; /* Lowest slot number below this Calgary */
47 u8 status; /* Bit 0 = 1 : the XAPIC is used */ 47 u8 status; /* Bit 0 = 1 : the XAPIC is used */
48 /* = 0 : the XAPIC is not used, ie: */ 48 /* = 0 : the XAPIC is not used, ie: */
49 /* ints fwded to another XAPIC */ 49 /* ints fwded to another XAPIC */
50 /* Bits1:7 Reserved */ 50 /* Bits1:7 Reserved */
51 u8 WP_index; /* instance index - lower ones have */ 51 u8 WP_index; /* instance index - lower ones have */
52 /* lower slot numbers/PCI bus numbers */ 52 /* lower slot numbers/PCI bus numbers */
53 u8 chassis_num; /* 1 based Chassis number */ 53 u8 chassis_num; /* 1 based Chassis number */
54} __attribute__((packed)); 54} __attribute__((packed));
55 55
56enum { 56enum {
57 HURR_SCALABILTY = 0, /* Hurricane Scalability info */ 57 HURR_SCALABILTY = 0, /* Hurricane Scalability info */
58 HURR_RIOIB = 2, /* Hurricane RIOIB info */ 58 HURR_RIOIB = 2, /* Hurricane RIOIB info */
59 COMPAT_CALGARY = 4, /* Compatibility Calgary */ 59 COMPAT_CALGARY = 4, /* Compatibility Calgary */
60 ALT_CALGARY = 5, /* Second Planar Calgary */ 60 ALT_CALGARY = 5, /* Second Planar Calgary */
61}; 61};
62 62
63/* 63/*
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