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authorMarkus Metzger <markus.t.metzger@intel.com>2008-01-30 07:31:09 -0500
committerIngo Molnar <mingo@elte.hu>2008-01-30 07:31:09 -0500
commiteee3af4a2c83a97fff107ddc445d9df6fded9ce4 (patch)
treea7e9179b82b4df9e4cf6e810c54309324589395b /include/asm-x86/processor_64.h
parent7796931f542518092d1fd2fb7cf1f1d96e0cd4b5 (diff)
x86, ptrace: support for branch trace store(BTS)
Resend using different mail client Changes to the last version: - split implementation into two layers: ds/bts and ptrace - renamed TIF's - save/restore ds save area msr in __switch_to_xtra() - make block-stepping only look at BTF bit Signed-off-by: Markus Metzger <markus.t.metzger@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-x86/processor_64.h')
-rw-r--r--include/asm-x86/processor_64.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-x86/processor_64.h b/include/asm-x86/processor_64.h
index 0780f3e3fdfe..7b7f8a142e20 100644
--- a/include/asm-x86/processor_64.h
+++ b/include/asm-x86/processor_64.h
@@ -240,6 +240,9 @@ struct thread_struct {
240 unsigned io_bitmap_max; 240 unsigned io_bitmap_max;
241/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */ 241/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
242 unsigned long debugctlmsr; 242 unsigned long debugctlmsr;
243/* Debug Store - if not 0 points to a DS Save Area configuration;
244 * goes into MSR_IA32_DS_AREA */
245 unsigned long ds_area_msr;
243/* cached TLS descriptors. */ 246/* cached TLS descriptors. */
244 u64 tls_array[GDT_ENTRY_TLS_ENTRIES]; 247 u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
245} __attribute__((aligned(16))); 248} __attribute__((aligned(16)));