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authorRichard Kennedy <richard@rsk.demon.co.uk>2008-07-04 08:56:16 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-04 10:47:19 -0400
commit84e65b0a84a2c856bef36f13d122047678408b0a (patch)
tree62d2e2e29fa107b3a04cd9156358639ec1e83cd3 /include/asm-x86/processor.h
parent95c60b08c6af6db2165837139da10f593462d51c (diff)
x86: cacheline_align tss_struct
The manual padding to align on cacheline size only worked in 32 bit In 64 bit the structure was not aligned and contained wasted space. use the compiler ____cachline_aligned to save space & properly align this structure. x86_64_default size goes from 9136 -> 8960 x86_64_AMD size goes from 9136 -> 8896 built & running on 2.6.26-rc8. Signed-off-by: Richard Kennedy <richard@rsk.demon.co.uk> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/processor.h')
-rw-r--r--include/asm-x86/processor.h6
1 files changed, 1 insertions, 5 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 559105220a47..4ab2ede6f4b9 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -263,15 +263,11 @@ struct tss_struct {
263 struct thread_struct *io_bitmap_owner; 263 struct thread_struct *io_bitmap_owner;
264 264
265 /* 265 /*
266 * Pad the TSS to be cacheline-aligned (size is 0x100):
267 */
268 unsigned long __cacheline_filler[35];
269 /*
270 * .. and then another 0x100 bytes for the emergency kernel stack: 266 * .. and then another 0x100 bytes for the emergency kernel stack:
271 */ 267 */
272 unsigned long stack[64]; 268 unsigned long stack[64];
273 269
274} __attribute__((packed)); 270} ____cacheline_aligned;
275 271
276DECLARE_PER_CPU(struct tss_struct, init_tss); 272DECLARE_PER_CPU(struct tss_struct, init_tss);
277 273