x86: use the same pgd_list for PAE and 64-bit

Use a standard list threaded through page->lru for maintaining the pgd
list on PAE.  This is the same as 64-bit, and seems saner than using a
non-standard list via page->index.

Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

1 files changed, 0 insertions, 3 deletions

diff --git a/include/asm-x86/pgtable_64.h b/include/asm-x86/pgtable_64.h
index ce1dbab75e39..6e615a103c2f 100644
--- a/include/asm-x86/pgtable_64.h
+++ b/include/asm-x86/pgtable_64.h
@@ -240,9 +240,6 @@ static inline unsigned long pmd_bad(pmd_t pmd)
 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)           ((pte_t) { .pte = (x).val })
 
-extern spinlock_t pgd_lock;
-extern struct list_head pgd_list;
-
 extern int kern_addr_valid(unsigned long addr); 
 
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \