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authorJeremy Fitzhardinge <jeremy@goop.org>2008-01-30 07:34:11 -0500
committerIngo Molnar <mingo@elte.hu>2008-01-30 07:34:11 -0500
commit6194ba6ff6ccf8d5c54c857600843c67aa82c407 (patch)
tree657dd9f452b252260fcf59959c0586920b8fe4c3 /include/asm-x86/pgtable-3level.h
parentfd40d6e3188b12c59696d6cb4a6f26333814d66f (diff)
x86: don't special-case pmd allocations as much
In x86 PAE mode, stop treating pmds as a special case. Previously they were always allocated and freed with the pgd. The modifies the code to be the same as 64-bit mode, where they are allocated on demand. This is a step on the way to unifying 32/64-bit pagetable allocation as much as possible. There is a complicating wart, however. When you install a new reference to a pmd in the pgd, the processor isn't guaranteed to see it unless you reload cr3. Since reloading cr3 also has the side-effect of flushing the tlb, this is an expense that we want to avoid whereever possible. This patch simply avoids reloading cr3 unless the update is to the current pagetable. Later patches will optimise this further. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: Andi Kleen <ak@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: William Irwin <wli@holomorphy.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-x86/pgtable-3level.h')
-rw-r--r--include/asm-x86/pgtable-3level.h39
1 files changed, 28 insertions, 11 deletions
diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h
index 62a1ffbc8784..ed4c6f0e57ec 100644
--- a/include/asm-x86/pgtable-3level.h
+++ b/include/asm-x86/pgtable-3level.h
@@ -15,9 +15,19 @@
15#define pgd_ERROR(e) \ 15#define pgd_ERROR(e) \
16 printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) 16 printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
17 17
18#define pud_none(pud) 0 18
19#define pud_bad(pud) 0 19static inline int pud_none(pud_t pud)
20#define pud_present(pud) 1 20{
21 return pud_val(pud) == 0;
22}
23static inline int pud_bad(pud_t pud)
24{
25 return (pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER)) != 0;
26}
27static inline int pud_present(pud_t pud)
28{
29 return pud_val(pud) & _PAGE_PRESENT;
30}
21 31
22/* Rules for using set_pte: the pte being assigned *must* be 32/* Rules for using set_pte: the pte being assigned *must* be
23 * either not present or in a state where the hardware will 33 * either not present or in a state where the hardware will
@@ -58,7 +68,7 @@ static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
58} 68}
59static inline void native_set_pud(pud_t *pudp, pud_t pud) 69static inline void native_set_pud(pud_t *pudp, pud_t pud)
60{ 70{
61 *pudp = pud; 71 set_64bit((unsigned long long *)(pudp),native_pud_val(pud));
62} 72}
63 73
64/* 74/*
@@ -81,13 +91,20 @@ static inline void native_pmd_clear(pmd_t *pmd)
81 *(tmp + 1) = 0; 91 *(tmp + 1) = 0;
82} 92}
83 93
84/* 94static inline void pud_clear(pud_t *pudp)
85 * Pentium-II erratum A13: in PAE mode we explicitly have to flush 95{
86 * the TLB via cr3 if the top-level pgd is changed... 96 set_pud(pudp, __pud(0));
87 * We do not let the generic code free and clear pgd entries due to 97
88 * this erratum. 98 /*
89 */ 99 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
90static inline void pud_clear (pud_t * pud) { } 100 * the TLB via cr3 if the top-level pgd is changed...
101 *
102 * XXX I don't think we need to worry about this here, since
103 * when clearing the pud, the calling code needs to flush the
104 * tlb anyway. But do it now for safety's sake. - jsgf
105 */
106 write_cr3(read_cr3());
107}
91 108
92#define pud_page(pud) \ 109#define pud_page(pud) \
93((struct page *) __va(pud_val(pud) & PAGE_MASK)) 110((struct page *) __va(pud_val(pud) & PAGE_MASK))