diff options
author | David Woodhouse <David.Woodhouse@intel.com> | 2008-10-13 12:13:56 -0400 |
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committer | David Woodhouse <David.Woodhouse@intel.com> | 2008-10-13 12:13:56 -0400 |
commit | e758936e02700ff88a0b08b722a3847b95283ef2 (patch) | |
tree | 50c919bef1b459a778b85159d5929de95b6c4a01 /include/asm-x86/msr-index.h | |
parent | 239cfbde1f5843c4a24199f117d5f67f637d72d5 (diff) | |
parent | 4480f15b3306f43bbb0310d461142b4e897ca45b (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
include/asm-x86/statfs.h
Diffstat (limited to 'include/asm-x86/msr-index.h')
-rw-r--r-- | include/asm-x86/msr-index.h | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h index 44bce773012e..0bb43301a202 100644 --- a/include/asm-x86/msr-index.h +++ b/include/asm-x86/msr-index.h | |||
@@ -1,5 +1,5 @@ | |||
1 | #ifndef __ASM_MSR_INDEX_H | 1 | #ifndef ASM_X86__MSR_INDEX_H |
2 | #define __ASM_MSR_INDEX_H | 2 | #define ASM_X86__MSR_INDEX_H |
3 | 3 | ||
4 | /* CPU model specific register (MSR) numbers */ | 4 | /* CPU model specific register (MSR) numbers */ |
5 | 5 | ||
@@ -176,6 +176,7 @@ | |||
176 | #define MSR_IA32_TSC 0x00000010 | 176 | #define MSR_IA32_TSC 0x00000010 |
177 | #define MSR_IA32_PLATFORM_ID 0x00000017 | 177 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
178 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a | 178 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
179 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a | ||
179 | 180 | ||
180 | #define MSR_IA32_APICBASE 0x0000001b | 181 | #define MSR_IA32_APICBASE 0x0000001b |
181 | #define MSR_IA32_APICBASE_BSP (1<<8) | 182 | #define MSR_IA32_APICBASE_BSP (1<<8) |
@@ -310,4 +311,19 @@ | |||
310 | /* Geode defined MSRs */ | 311 | /* Geode defined MSRs */ |
311 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 | 312 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
312 | 313 | ||
313 | #endif /* __ASM_MSR_INDEX_H */ | 314 | /* Intel VT MSRs */ |
315 | #define MSR_IA32_VMX_BASIC 0x00000480 | ||
316 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | ||
317 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | ||
318 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | ||
319 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | ||
320 | #define MSR_IA32_VMX_MISC 0x00000485 | ||
321 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | ||
322 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | ||
323 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | ||
324 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | ||
325 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | ||
326 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | ||
327 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | ||
328 | |||
329 | #endif /* ASM_X86__MSR_INDEX_H */ | ||