diff options
author | Sheng Yang <sheng.yang@intel.com> | 2008-09-09 02:54:53 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-09-10 08:00:55 -0400 |
commit | 315a6558f30a264c88274fa70626615d1c7851c7 (patch) | |
tree | 39849101166813a27a837b20776bb5b31681d7ef /include/asm-x86/msr-index.h | |
parent | 59c37bf8924c30fbac7ebb66a1d92dcb9f05f6b1 (diff) |
x86: move VMX MSRs to msr-index.h
They are hardware specific MSRs, and we would use them in virtualization
feature detection later.
Signed-off-by: Sheng Yang <sheng.yang@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/msr-index.h')
-rw-r--r-- | include/asm-x86/msr-index.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h index 3052f058ab06..0bb43301a202 100644 --- a/include/asm-x86/msr-index.h +++ b/include/asm-x86/msr-index.h | |||
@@ -176,6 +176,7 @@ | |||
176 | #define MSR_IA32_TSC 0x00000010 | 176 | #define MSR_IA32_TSC 0x00000010 |
177 | #define MSR_IA32_PLATFORM_ID 0x00000017 | 177 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
178 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a | 178 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
179 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a | ||
179 | 180 | ||
180 | #define MSR_IA32_APICBASE 0x0000001b | 181 | #define MSR_IA32_APICBASE 0x0000001b |
181 | #define MSR_IA32_APICBASE_BSP (1<<8) | 182 | #define MSR_IA32_APICBASE_BSP (1<<8) |
@@ -310,4 +311,19 @@ | |||
310 | /* Geode defined MSRs */ | 311 | /* Geode defined MSRs */ |
311 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 | 312 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
312 | 313 | ||
314 | /* Intel VT MSRs */ | ||
315 | #define MSR_IA32_VMX_BASIC 0x00000480 | ||
316 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | ||
317 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | ||
318 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | ||
319 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | ||
320 | #define MSR_IA32_VMX_MISC 0x00000485 | ||
321 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | ||
322 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | ||
323 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | ||
324 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | ||
325 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | ||
326 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | ||
327 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | ||
328 | |||
313 | #endif /* ASM_X86__MSR_INDEX_H */ | 329 | #endif /* ASM_X86__MSR_INDEX_H */ |