diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2008-05-02 14:10:09 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-05-12 15:28:05 -0400 |
commit | 9b7dc567d03d74a1fbae84e88949b6a60d922d82 (patch) | |
tree | 7b59581c40ea13373574daeb53a01e90729ddc7f /include/asm-x86/mach-voyager | |
parent | 2e0884362d1fe36ef2d673d763d6ce35e2044e66 (diff) |
x86: unify interrupt vector defines
The interrupt vector defines are copied 4 times around with minimal
differences. Move them all into asm-x86/irq_vectors.h
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/mach-voyager')
-rw-r--r-- | include/asm-x86/mach-voyager/irq_vectors.h | 79 |
1 files changed, 0 insertions, 79 deletions
diff --git a/include/asm-x86/mach-voyager/irq_vectors.h b/include/asm-x86/mach-voyager/irq_vectors.h deleted file mode 100644 index 165421f5821c..000000000000 --- a/include/asm-x86/mach-voyager/irq_vectors.h +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | /* -*- mode: c; c-basic-offset: 8 -*- */ | ||
2 | |||
3 | /* Copyright (C) 2002 | ||
4 | * | ||
5 | * Author: James.Bottomley@HansenPartnership.com | ||
6 | * | ||
7 | * linux/arch/i386/voyager/irq_vectors.h | ||
8 | * | ||
9 | * This file provides definitions for the VIC and QIC CPIs | ||
10 | */ | ||
11 | |||
12 | #ifndef _ASM_IRQ_VECTORS_H | ||
13 | #define _ASM_IRQ_VECTORS_H | ||
14 | |||
15 | /* | ||
16 | * IDT vectors usable for external interrupt sources start | ||
17 | * at 0x20: | ||
18 | */ | ||
19 | #define FIRST_EXTERNAL_VECTOR 0x20 | ||
20 | |||
21 | #define SYSCALL_VECTOR 0x80 | ||
22 | |||
23 | /* | ||
24 | * Vectors 0x20-0x2f are used for ISA interrupts. | ||
25 | */ | ||
26 | |||
27 | /* These define the CPIs we use in linux */ | ||
28 | #define VIC_CPI_LEVEL0 0 | ||
29 | #define VIC_CPI_LEVEL1 1 | ||
30 | /* now the fake CPIs */ | ||
31 | #define VIC_TIMER_CPI 2 | ||
32 | #define VIC_INVALIDATE_CPI 3 | ||
33 | #define VIC_RESCHEDULE_CPI 4 | ||
34 | #define VIC_ENABLE_IRQ_CPI 5 | ||
35 | #define VIC_CALL_FUNCTION_CPI 6 | ||
36 | |||
37 | /* Now the QIC CPIs: Since we don't need the two initial levels, | ||
38 | * these are 2 less than the VIC CPIs */ | ||
39 | #define QIC_CPI_OFFSET 1 | ||
40 | #define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET) | ||
41 | #define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET) | ||
42 | #define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET) | ||
43 | #define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET) | ||
44 | #define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET) | ||
45 | |||
46 | #define VIC_START_FAKE_CPI VIC_TIMER_CPI | ||
47 | #define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_CPI | ||
48 | |||
49 | /* this is the SYS_INT CPI. */ | ||
50 | #define VIC_SYS_INT 8 | ||
51 | #define VIC_CMN_INT 15 | ||
52 | |||
53 | /* This is the boot CPI for alternate processors. It gets overwritten | ||
54 | * by the above once the system has activated all available processors */ | ||
55 | #define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0 | ||
56 | #define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8) | ||
57 | |||
58 | #define NR_VECTORS 256 | ||
59 | #define NR_IRQS 224 | ||
60 | #define NR_IRQ_VECTORS NR_IRQS | ||
61 | |||
62 | #define FPU_IRQ 13 | ||
63 | |||
64 | #define FIRST_VM86_IRQ 3 | ||
65 | #define LAST_VM86_IRQ 15 | ||
66 | #define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) | ||
67 | |||
68 | #ifndef __ASSEMBLY__ | ||
69 | extern asmlinkage void vic_cpi_interrupt(void); | ||
70 | extern asmlinkage void vic_sys_interrupt(void); | ||
71 | extern asmlinkage void vic_cmn_interrupt(void); | ||
72 | extern asmlinkage void qic_timer_interrupt(void); | ||
73 | extern asmlinkage void qic_invalidate_interrupt(void); | ||
74 | extern asmlinkage void qic_reschedule_interrupt(void); | ||
75 | extern asmlinkage void qic_enable_irq_interrupt(void); | ||
76 | extern asmlinkage void qic_call_function_interrupt(void); | ||
77 | #endif /* !__ASSEMBLY__ */ | ||
78 | |||
79 | #endif /* _ASM_IRQ_VECTORS_H */ | ||