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authorThomas Gleixner <tglx@linutronix.de>2007-10-11 05:20:03 -0400
committerThomas Gleixner <tglx@linutronix.de>2007-10-11 05:20:03 -0400
commit96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42 (patch)
treed947a467aa2da3140279617bc4b9b101640d7bf4 /include/asm-x86/mach-summit
parent27bd0c955648646abf2a353a8371d28c37bcd982 (diff)
i386/x86_64: move headers to include/asm-x86
Move the headers to include/asm-x86 and fixup the header install make rules Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/mach-summit')
-rw-r--r--include/asm-x86/mach-summit/irq_vectors_limits.h14
-rw-r--r--include/asm-x86/mach-summit/mach_apic.h197
-rw-r--r--include/asm-x86/mach-summit/mach_apicdef.h13
-rw-r--r--include/asm-x86/mach-summit/mach_ipi.h25
-rw-r--r--include/asm-x86/mach-summit/mach_mpparse.h121
-rw-r--r--include/asm-x86/mach-summit/mach_mpspec.h9
6 files changed, 379 insertions, 0 deletions
diff --git a/include/asm-x86/mach-summit/irq_vectors_limits.h b/include/asm-x86/mach-summit/irq_vectors_limits.h
new file mode 100644
index 000000000000..890ce3f5e09a
--- /dev/null
+++ b/include/asm-x86/mach-summit/irq_vectors_limits.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_IRQ_VECTORS_LIMITS_H
2#define _ASM_IRQ_VECTORS_LIMITS_H
3
4/*
5 * For Summit or generic (i.e. installer) kernels, we have lots of I/O APICs,
6 * even with uni-proc kernels, so use a big array.
7 *
8 * This value should be the same in both the generic and summit subarches.
9 * Change one, change 'em both.
10 */
11#define NR_IRQS 224
12#define NR_IRQ_VECTORS 1024
13
14#endif /* _ASM_IRQ_VECTORS_LIMITS_H */
diff --git a/include/asm-x86/mach-summit/mach_apic.h b/include/asm-x86/mach-summit/mach_apic.h
new file mode 100644
index 000000000000..732f776aab8e
--- /dev/null
+++ b/include/asm-x86/mach-summit/mach_apic.h
@@ -0,0 +1,197 @@
1#ifndef __ASM_MACH_APIC_H
2#define __ASM_MACH_APIC_H
3
4#include <asm/smp.h>
5
6#define esr_disable (1)
7#define NO_BALANCE_IRQ (0)
8
9/* In clustered mode, the high nibble of APIC ID is a cluster number.
10 * The low nibble is a 4-bit bitmap. */
11#define XAPIC_DEST_CPUS_SHIFT 4
12#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
13#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
14
15#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
16
17static inline cpumask_t target_cpus(void)
18{
19 /* CPU_MASK_ALL (0xff) has undefined behaviour with
20 * dest_LowestPrio mode logical clustered apic interrupt routing
21 * Just start on cpu 0. IRQ balancing will spread load
22 */
23 return cpumask_of_cpu(0);
24}
25#define TARGET_CPUS (target_cpus())
26
27#define INT_DELIVERY_MODE (dest_LowestPrio)
28#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
29
30static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
31{
32 return 0;
33}
34
35/* we don't use the phys_cpu_present_map to indicate apicid presence */
36static inline unsigned long check_apicid_present(int bit)
37{
38 return 1;
39}
40
41#define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
42
43extern u8 bios_cpu_apicid[];
44extern u8 cpu_2_logical_apicid[];
45
46static inline void init_apic_ldr(void)
47{
48 unsigned long val, id;
49 int count = 0;
50 u8 my_id = (u8)hard_smp_processor_id();
51 u8 my_cluster = (u8)apicid_cluster(my_id);
52#ifdef CONFIG_SMP
53 u8 lid;
54 int i;
55
56 /* Create logical APIC IDs by counting CPUs already in cluster. */
57 for (count = 0, i = NR_CPUS; --i >= 0; ) {
58 lid = cpu_2_logical_apicid[i];
59 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
60 ++count;
61 }
62#endif
63 /* We only have a 4 wide bitmap in cluster mode. If a deranged
64 * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
65 BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
66 id = my_cluster | (1UL << count);
67 apic_write_around(APIC_DFR, APIC_DFR_VALUE);
68 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
69 val |= SET_APIC_LOGICAL_ID(id);
70 apic_write_around(APIC_LDR, val);
71}
72
73static inline int multi_timer_check(int apic, int irq)
74{
75 return 0;
76}
77
78static inline int apic_id_registered(void)
79{
80 return 1;
81}
82
83static inline void setup_apic_routing(void)
84{
85 printk("Enabling APIC mode: Summit. Using %d I/O APICs\n",
86 nr_ioapics);
87}
88
89static inline int apicid_to_node(int logical_apicid)
90{
91#ifdef CONFIG_SMP
92 return apicid_2_node[hard_smp_processor_id()];
93#else
94 return 0;
95#endif
96}
97
98/* Mapping from cpu number to logical apicid */
99static inline int cpu_to_logical_apicid(int cpu)
100{
101#ifdef CONFIG_SMP
102 if (cpu >= NR_CPUS)
103 return BAD_APICID;
104 return (int)cpu_2_logical_apicid[cpu];
105#else
106 return logical_smp_processor_id();
107#endif
108}
109
110static inline int cpu_present_to_apicid(int mps_cpu)
111{
112 if (mps_cpu < NR_CPUS)
113 return (int)bios_cpu_apicid[mps_cpu];
114 else
115 return BAD_APICID;
116}
117
118static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
119{
120 /* For clustered we don't have a good way to do this yet - hack */
121 return physids_promote(0x0F);
122}
123
124static inline physid_mask_t apicid_to_cpu_present(int apicid)
125{
126 return physid_mask_of_physid(0);
127}
128
129static inline int mpc_apic_id(struct mpc_config_processor *m,
130 struct mpc_config_translation *translation_record)
131{
132 printk("Processor #%d %ld:%ld APIC version %d\n",
133 m->mpc_apicid,
134 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
135 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
136 m->mpc_apicver);
137 return (m->mpc_apicid);
138}
139
140static inline void setup_portio_remap(void)
141{
142}
143
144static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
145{
146 return 1;
147}
148
149static inline void enable_apic_mode(void)
150{
151}
152
153static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
154{
155 int num_bits_set;
156 int cpus_found = 0;
157 int cpu;
158 int apicid;
159
160 num_bits_set = cpus_weight(cpumask);
161 /* Return id to all */
162 if (num_bits_set == NR_CPUS)
163 return (int) 0xFF;
164 /*
165 * The cpus in the mask must all be on the apic cluster. If are not
166 * on the same apicid cluster return default value of TARGET_CPUS.
167 */
168 cpu = first_cpu(cpumask);
169 apicid = cpu_to_logical_apicid(cpu);
170 while (cpus_found < num_bits_set) {
171 if (cpu_isset(cpu, cpumask)) {
172 int new_apicid = cpu_to_logical_apicid(cpu);
173 if (apicid_cluster(apicid) !=
174 apicid_cluster(new_apicid)){
175 printk ("%s: Not a valid mask!\n",__FUNCTION__);
176 return 0xFF;
177 }
178 apicid = apicid | new_apicid;
179 cpus_found++;
180 }
181 cpu++;
182 }
183 return apicid;
184}
185
186/* cpuid returns the value latched in the HW at reset, not the APIC ID
187 * register's value. For any box whose BIOS changes APIC IDs, like
188 * clustered APIC systems, we must use hard_smp_processor_id.
189 *
190 * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
191 */
192static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
193{
194 return hard_smp_processor_id() >> index_msb;
195}
196
197#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-x86/mach-summit/mach_apicdef.h b/include/asm-x86/mach-summit/mach_apicdef.h
new file mode 100644
index 000000000000..a58ab5a75c8c
--- /dev/null
+++ b/include/asm-x86/mach-summit/mach_apicdef.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_MACH_APICDEF_H
2#define __ASM_MACH_APICDEF_H
3
4#define APIC_ID_MASK (0xFF<<24)
5
6static inline unsigned get_apic_id(unsigned long x)
7{
8 return (((x)>>24)&0xFF);
9}
10
11#define GET_APIC_ID(x) get_apic_id(x)
12
13#endif
diff --git a/include/asm-x86/mach-summit/mach_ipi.h b/include/asm-x86/mach-summit/mach_ipi.h
new file mode 100644
index 000000000000..9404c535b7ec
--- /dev/null
+++ b/include/asm-x86/mach-summit/mach_ipi.h
@@ -0,0 +1,25 @@
1#ifndef __ASM_MACH_IPI_H
2#define __ASM_MACH_IPI_H
3
4void send_IPI_mask_sequence(cpumask_t mask, int vector);
5
6static inline void send_IPI_mask(cpumask_t mask, int vector)
7{
8 send_IPI_mask_sequence(mask, vector);
9}
10
11static inline void send_IPI_allbutself(int vector)
12{
13 cpumask_t mask = cpu_online_map;
14 cpu_clear(smp_processor_id(), mask);
15
16 if (!cpus_empty(mask))
17 send_IPI_mask(mask, vector);
18}
19
20static inline void send_IPI_all(int vector)
21{
22 send_IPI_mask(cpu_online_map, vector);
23}
24
25#endif /* __ASM_MACH_IPI_H */
diff --git a/include/asm-x86/mach-summit/mach_mpparse.h b/include/asm-x86/mach-summit/mach_mpparse.h
new file mode 100644
index 000000000000..c2520539d934
--- /dev/null
+++ b/include/asm-x86/mach-summit/mach_mpparse.h
@@ -0,0 +1,121 @@
1#ifndef __ASM_MACH_MPPARSE_H
2#define __ASM_MACH_MPPARSE_H
3
4#include <mach_apic.h>
5#include <asm/tsc.h>
6
7extern int use_cyclone;
8
9#ifdef CONFIG_X86_SUMMIT_NUMA
10extern void setup_summit(void);
11#else
12#define setup_summit() {}
13#endif
14
15static inline void mpc_oem_bus_info(struct mpc_config_bus *m, char *name,
16 struct mpc_config_translation *translation)
17{
18 Dprintk("Bus #%d is %s\n", m->mpc_busid, name);
19}
20
21static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
22 struct mpc_config_translation *translation)
23{
24}
25
26static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
27 char *productid)
28{
29 if (!strncmp(oem, "IBM ENSW", 8) &&
30 (!strncmp(productid, "VIGIL SMP", 9)
31 || !strncmp(productid, "EXA", 3)
32 || !strncmp(productid, "RUTHLESS SMP", 12))){
33 mark_tsc_unstable("Summit based system");
34 use_cyclone = 1; /*enable cyclone-timer*/
35 setup_summit();
36 return 1;
37 }
38 return 0;
39}
40
41/* Hook from generic ACPI tables.c */
42static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
43{
44 if (!strncmp(oem_id, "IBM", 3) &&
45 (!strncmp(oem_table_id, "SERVIGIL", 8)
46 || !strncmp(oem_table_id, "EXA", 3))){
47 mark_tsc_unstable("Summit based system");
48 use_cyclone = 1; /*enable cyclone-timer*/
49 setup_summit();
50 return 1;
51 }
52 return 0;
53}
54
55struct rio_table_hdr {
56 unsigned char version; /* Version number of this data structure */
57 /* Version 3 adds chassis_num & WP_index */
58 unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */
59 unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */
60} __attribute__((packed));
61
62struct scal_detail {
63 unsigned char node_id; /* Scalability Node ID */
64 unsigned long CBAR; /* Address of 1MB register space */
65 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
66 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
67 unsigned char port1node; /* Node ID port connected to: 0xFF = None */
68 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
69 unsigned char port2node; /* Node ID port connected to: 0xFF = None */
70 unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */
71 unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */
72} __attribute__((packed));
73
74struct rio_detail {
75 unsigned char node_id; /* RIO Node ID */
76 unsigned long BBAR; /* Address of 1MB register space */
77 unsigned char type; /* Type of device */
78 unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/
79 /* For CYC: Node ID of Twister that owns this CYC */
80 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
81 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
82 unsigned char port1node; /* Node ID port connected to: 0xFF=None */
83 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
84 unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */
85 /* For CYC: 0 */
86 unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */
87 /* = 0 : the XAPIC is not used, ie:*/
88 /* ints fwded to another XAPIC */
89 /* Bits1:7 Reserved */
90 /* For CYC: Bits0:7 Reserved */
91 unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */
92 /* lower slot numbers/PCI bus numbers */
93 /* For CYC: No meaning */
94 unsigned char chassis_num; /* 1 based Chassis number */
95 /* For LookOut WPEGs this field indicates the */
96 /* Expansion Chassis #, enumerated from Boot */
97 /* Node WPEG external port, then Boot Node CYC */
98 /* external port, then Next Vigil chassis WPEG */
99 /* external port, etc. */
100 /* Shared Lookouts have only 1 chassis number (the */
101 /* first one assigned) */
102} __attribute__((packed));
103
104
105typedef enum {
106 CompatTwister = 0, /* Compatibility Twister */
107 AltTwister = 1, /* Alternate Twister of internal 8-way */
108 CompatCyclone = 2, /* Compatibility Cyclone */
109 AltCyclone = 3, /* Alternate Cyclone of internal 8-way */
110 CompatWPEG = 4, /* Compatibility WPEG */
111 AltWPEG = 5, /* Second Planar WPEG */
112 LookOutAWPEG = 6, /* LookOut WPEG */
113 LookOutBWPEG = 7, /* LookOut WPEG */
114} node_type;
115
116static inline int is_WPEG(struct rio_detail *rio){
117 return (rio->type == CompatWPEG || rio->type == AltWPEG ||
118 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
119}
120
121#endif /* __ASM_MACH_MPPARSE_H */
diff --git a/include/asm-x86/mach-summit/mach_mpspec.h b/include/asm-x86/mach-summit/mach_mpspec.h
new file mode 100644
index 000000000000..bd765523511a
--- /dev/null
+++ b/include/asm-x86/mach-summit/mach_mpspec.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_MACH_MPSPEC_H
2#define __ASM_MACH_MPSPEC_H
3
4#define MAX_IRQ_SOURCES 256
5
6/* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. */
7#define MAX_MP_BUSSES 260
8
9#endif /* __ASM_MACH_MPSPEC_H */