aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-x86/cpufeature.h
diff options
context:
space:
mode:
authorH. Peter Anvin <hpa@zytor.com>2008-08-28 00:20:07 -0400
committerH. Peter Anvin <hpa@zytor.com>2008-08-28 00:20:07 -0400
commit2798c63e65cb0f05cc12a060b9b0d56ac9523c4d (patch)
tree9346dc2f9bec4d0bdeba7b3067056cfde48c67f7 /include/asm-x86/cpufeature.h
parentf1240c002679a77990fd7c198991ed15a437d691 (diff)
x86: <asm/cpufeature.h>: clean up overlong lines, whitespace
Clean up overlong lines and stealth whitespace in <asm-x86/cpufeature.h>. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'include/asm-x86/cpufeature.h')
-rw-r--r--include/asm-x86/cpufeature.h11
1 files changed, 6 insertions, 5 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 7bd98b724fd5..7710686c11f9 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -20,7 +20,7 @@
20#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ 20#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
21#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ 21#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
22#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ 22#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
23#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ 23#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */
24#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ 24#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
25#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ 25#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
26#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ 26#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
@@ -29,11 +29,12 @@
29#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ 29#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
30#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ 30#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
31#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ 31#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
32#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ 32#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */
33 /* (plus FCMOVcc, FCOMI with FPU) */
33#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ 34#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
34#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ 35#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
35#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ 36#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
36#define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" Supports the CLFLUSH instruction */ 37#define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */
37#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ 38#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */
38#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ 39#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
39#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 40#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
@@ -83,7 +84,7 @@
83#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 84#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
84#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ 85#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */
85#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ 86#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */
86#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ 87#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
87#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ 88#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
88#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ 89#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
89#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ 90#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */
@@ -181,7 +182,7 @@ extern const char * const x86_power_flags[32];
181} while (0) 182} while (0)
182#define setup_force_cpu_cap(bit) do { \ 183#define setup_force_cpu_cap(bit) do { \
183 set_cpu_cap(&boot_cpu_data, bit); \ 184 set_cpu_cap(&boot_cpu_data, bit); \
184 clear_bit(bit, (unsigned long *)cleared_cpu_caps); \ 185 clear_bit(bit, (unsigned long *)cleared_cpu_caps); \
185} while (0) 186} while (0)
186 187
187#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) 188#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)