[SPARC64]: Probe D/I/E-cache config and use.

At boot time, determine the D-cache, I-cache and E-cache size and
line-size.  Use them in cache flushes when appropriate.

This change was motivated by discovering that the D-cache on
UltraSparc-IIIi and later are 64K not 32K, and the flushes done by the
Cheetah error handlers were assuming a 32K size.

There are still some pieces of code that are hard coding things and
will need to be fixed up at some point.

While we're here, fix the D-cache and I-cache parity error handlers
to run with interrupts disabled, and when the trap occurs at trap
level > 1 log the event via a counter displayed in /proc/cpuinfo.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 10 insertions, 0 deletions

diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index 9a3a81f1cc58..74de79dca915 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -22,6 +22,16 @@ typedef struct {
         unsigned int    __pad1;
         unsigned long   *pte_cache[2];
         unsigned long   *pgd_cache;
+
+        /* Dcache line 3, rarely used */
+        unsigned int    dcache_size;
+        unsigned int    dcache_line_size;
+        unsigned int    icache_size;
+        unsigned int    icache_line_size;
+        unsigned int    ecache_size;
+        unsigned int    ecache_line_size;
+        unsigned int    __pad2;
+        unsigned int    __pad3;
 } cpuinfo_sparc;
 
 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);