Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

6 files changed, 32 insertions, 26 deletions

diff --git a/include/asm-sparc64/auxio.h b/include/asm-sparc64/auxio.h
index 5eb01dd47150..81a590a50a1f 100644
--- a/include/asm-sparc64/auxio.h
+++ b/include/asm-sparc64/auxio.h
@@ -75,6 +75,8 @@
 
 #ifndef __ASSEMBLY__
 
+extern void __iomem *auxio_register;
+
 #define AUXIO_LTE_ON    1
 #define AUXIO_LTE_OFF   0
 
diff --git a/include/asm-sparc64/floppy.h b/include/asm-sparc64/floppy.h
index e071b4b4edfd..49d49a285943 100644
--- a/include/asm-sparc64/floppy.h
+++ b/include/asm-sparc64/floppy.h
@@ -159,7 +159,7 @@ static void sun_82077_fd_outb(unsigned char value, unsigned long port)
  * underruns.  If non-zero, doing_pdma encodes the direction of
  * the transfer for debugging.  1=read 2=write
  */
-char *pdma_vaddr;
+unsigned char *pdma_vaddr;
 unsigned long pdma_size;
 volatile int doing_pdma = 0;
 
@@ -209,8 +209,7 @@ static void sun_fd_enable_dma(void)
         pdma_areasize = pdma_size;
 }
 
-/* Our low-level entry point in arch/sparc/kernel/entry.S */
-extern irqreturn_t floppy_hardint(int irq, void *unused, struct pt_regs *regs);
+extern irqreturn_t sparc_floppy_irq(int, void *, struct pt_regs *);
 
 static int sun_fd_request_irq(void)
 {
@@ -220,8 +219,8 @@ static int sun_fd_request_irq(void)
         if(!once) {
                 once = 1;
 
-                error = request_fast_irq(FLOPPY_IRQ, floppy_hardint, 
-                                         SA_INTERRUPT, "floppy", NULL);
+                error = request_irq(FLOPPY_IRQ, sparc_floppy_irq, 
+                                    SA_INTERRUPT, "floppy", NULL);
 
                 return ((error == 0) ? 0 : -1);
         }
@@ -615,7 +614,7 @@ static unsigned long __init sun_floppy_init(void)
                 struct linux_ebus *ebus;
                 struct linux_ebus_device *edev = NULL;
                 unsigned long config = 0;
-                unsigned long auxio_reg;
+                void __iomem *auxio_reg;
 
                 for_each_ebus(ebus) {
                         for_each_ebusdev(edev, ebus) {
@@ -642,7 +641,7 @@ static unsigned long __init sun_floppy_init(void)
                 /* Make sure the high density bit is set, some systems
                  * (most notably Ultra5/Ultra10) come up with it clear.
                  */
-                auxio_reg = edev->resource[2].start;
+                auxio_reg = (void __iomem *) edev->resource[2].start;
                 writel(readl(auxio_reg)|0x2, auxio_reg);
 
                 sun_pci_ebus_dev = ebus->self;
@@ -650,7 +649,8 @@ static unsigned long __init sun_floppy_init(void)
                 spin_lock_init(&sun_pci_fd_ebus_dma.lock);
 
                 /* XXX ioremap */
-                sun_pci_fd_ebus_dma.regs = edev->resource[1].start;
+                sun_pci_fd_ebus_dma.regs = (void __iomem *)
+                        edev->resource[1].start;
                 if (!sun_pci_fd_ebus_dma.regs)
                         return 0;
 
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index 3aef0ca67750..018e2e46082b 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -19,7 +19,7 @@
 /* You should not mess with this directly. That's the job of irq.c.
  *
  * If you make changes here, please update hand coded assembler of
- * SBUS/floppy interrupt handler in entry.S -DaveM
+ * the vectored interrupt trap handler in entry.S -DaveM
  *
  * This is currently one DCACHE line, two buckets per L2 cache
  * line.  Keep this in mind please.
@@ -122,11 +122,6 @@ extern void enable_irq(unsigned int);
 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
 
-extern int request_fast_irq(unsigned int irq,
-                            irqreturn_t (*handler)(int, void *, struct pt_regs *),
-                            unsigned long flags, __const__ char *devname,
-                            void *dev_id);
-
 static __inline__ void set_softint(unsigned long bits)
 {
         __asm__ __volatile__("wr        %0, 0x0, %%set_softint"
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index bf2ae90ed3df..a1cc94f95984 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -55,8 +55,9 @@ static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
                 "add            %%g1, %1, %%g7\n\t"
                 "cas            [%2], %%g1, %%g7\n\t"
                 "cmp            %%g1, %%g7\n\t"
+                "membar         #StoreLoad | #StoreStore\n\t"
                 "bne,pn         %%icc, 1b\n\t"
-                " membar        #StoreLoad | #StoreStore\n\t"
+                " nop\n\t"
                 "mov            %%g7, %0\n\t"
                 : "=&r" (tmp)
                 : "0" (tmp), "r" (sem)
diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h
index db7581bdb531..9cb93a5c2b4f 100644
--- a/include/asm-sparc64/spinlock.h
+++ b/include/asm-sparc64/spinlock.h
@@ -52,12 +52,14 @@ static inline void _raw_spin_lock(spinlock_t *lock)
 
         __asm__ __volatile__(
 "1:     ldstub          [%1], %0\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       brnz,pn         %0, 2f\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     ldub            [%1], %0\n"
+"       membar          #LoadLoad\n"
 "       brnz,pt         %0, 2b\n"
-"        membar         #LoadLoad\n"
+"        nop\n"
 "       ba,a,pt         %%xcc, 1b\n"
 "       .previous"
         : "=&r" (tmp)
@@ -95,16 +97,18 @@ static inline void _raw_spin_lock_flags(spinlock_t *lock, unsigned long flags)
 
         __asm__ __volatile__(
 "1:     ldstub          [%2], %0\n"
-"       brnz,pn         %0, 2f\n"
 "       membar          #StoreLoad | #StoreStore\n"
+"       brnz,pn         %0, 2f\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     rdpr            %%pil, %1\n"
 "       wrpr            %3, %%pil\n"
 "3:     ldub            [%2], %0\n"
-"       brnz,pt         %0, 3b\n"
 "       membar          #LoadLoad\n"
+"       brnz,pt         %0, 3b\n"
+"        nop\n"
 "       ba,pt           %%xcc, 1b\n"
-"       wrpr            %1, %%pil\n"
+"        wrpr           %1, %%pil\n"
 "       .previous"
         : "=&r" (tmp1), "=&r" (tmp2)
         : "r"(lock), "r"(flags)
@@ -162,12 +166,14 @@ static void inline __read_lock(rwlock_t *lock)
 "4:      add            %0, 1, %1\n"
 "       cas             [%2], %0, %1\n"
 "       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       bne,pn          %%icc, 1b\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     ldsw            [%2], %0\n"
+"       membar          #LoadLoad\n"
 "       brlz,pt         %0, 2b\n"
-"        membar         #LoadLoad\n"
+"        nop\n"
 "       ba,a,pt         %%xcc, 4b\n"
 "       .previous"
         : "=&r" (tmp1), "=&r" (tmp2)
@@ -204,12 +210,14 @@ static void inline __write_lock(rwlock_t *lock)
 "4:      or             %0, %3, %1\n"
 "       cas             [%2], %0, %1\n"
 "       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       bne,pn          %%icc, 1b\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     lduw            [%2], %0\n"
+"       membar          #LoadLoad\n"
 "       brnz,pt         %0, 2b\n"
-"        membar         #LoadLoad\n"
+"        nop\n"
 "       ba,a,pt         %%xcc, 4b\n"
 "       .previous"
         : "=&r" (tmp1), "=&r" (tmp2)
@@ -240,8 +248,9 @@ static int inline __write_trylock(rwlock_t *lock)
 "        or             %0, %4, %1\n"
 "       cas             [%3], %0, %1\n"
 "       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       bne,pn          %%icc, 1b\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       mov             1, %2\n"
 "2:"
         : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index 9d7613eea812..1aa932773af8 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -111,7 +111,6 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
                              "membar    #Sync"
                              : /* No outputs */
                              : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
-        __asm__ __volatile__ ("membar #Sync" : : : "memory");
 }
 
 /* The instruction cache lines are flushed with this, but note that