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authorRavikiran G Thirumalai <kiran@scalex86.org>2006-01-08 04:01:28 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-08 23:13:39 -0500
commit1fd73c6b6737b7e6eacac1b00dac16e7540c3cb1 (patch)
treee66dbe34118b289c6f89a23764e355ea62fa2c62 /include/asm-sparc64
parent22fc6eccbf4ce4eb6265e6ada7b50a7b9cc57d05 (diff)
[PATCH] Kill L1_CACHE_SHIFT_MAX
Kill L1_CACHE_SHIFT from all arches. Since L1_CACHE_SHIFT_MAX is not used anymore with the introduction of INTERNODE_CACHE, kill L1_CACHE_SHIFT_MAX. Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org> Signed-off-by: Shai Fultheim <shai@scalex86.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-sparc64')
-rw-r--r--include/asm-sparc64/cache.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h
index ade5ec3bfd5a..f7d35a2ae9b8 100644
--- a/include/asm-sparc64/cache.h
+++ b/include/asm-sparc64/cache.h
@@ -9,7 +9,6 @@
9#define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */ 9#define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */
10 10
11#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 11#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
12#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
13 12
14#define SMP_CACHE_BYTES_SHIFT 6 13#define SMP_CACHE_BYTES_SHIFT 6
15#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */ 14#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */