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author | David S. Miller <davem@davemloft.net> | 2008-03-18 02:44:31 -0400 |
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committer | David S. Miller <davem@davemloft.net> | 2008-03-18 02:44:31 -0400 |
commit | 2f633928cbba8a5858bb39b11e7219a41b0fbef5 (patch) | |
tree | 9a82f4b7f2c3afe4b0208d8e44ea61bae90a7d22 /include/asm-sparc64 | |
parent | 5e226e4d9016daee170699f8a4188a5505021756 (diff) | |
parent | bde4f8fa8db2abd5ac9c542d76012d0fedab050f (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-sparc64')
-rw-r--r-- | include/asm-sparc64/kprobes.h | 2 | ||||
-rw-r--r-- | include/asm-sparc64/system.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-sparc64/kprobes.h b/include/asm-sparc64/kprobes.h index 7237dd87663e..5879d71afdaa 100644 --- a/include/asm-sparc64/kprobes.h +++ b/include/asm-sparc64/kprobes.h | |||
@@ -14,8 +14,6 @@ typedef u32 kprobe_opcode_t; | |||
14 | 14 | ||
15 | #define arch_remove_kprobe(p) do {} while (0) | 15 | #define arch_remove_kprobe(p) do {} while (0) |
16 | 16 | ||
17 | #define ARCH_SUPPORTS_KRETPROBES | ||
18 | |||
19 | #define flush_insn_slot(p) \ | 17 | #define flush_insn_slot(p) \ |
20 | do { flushi(&(p)->ainsn.insn[0]); \ | 18 | do { flushi(&(p)->ainsn.insn[0]); \ |
21 | flushi(&(p)->ainsn.insn[1]); \ | 19 | flushi(&(p)->ainsn.insn[1]); \ |
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h index ed91a5d8d4f0..53eae091a171 100644 --- a/include/asm-sparc64/system.h +++ b/include/asm-sparc64/system.h | |||
@@ -30,6 +30,8 @@ enum sparc_cpu { | |||
30 | #define ARCH_SUN4C_SUN4 0 | 30 | #define ARCH_SUN4C_SUN4 0 |
31 | #define ARCH_SUN4 0 | 31 | #define ARCH_SUN4 0 |
32 | 32 | ||
33 | extern char reboot_command[]; | ||
34 | |||
33 | /* These are here in an effort to more fully work around Spitfire Errata | 35 | /* These are here in an effort to more fully work around Spitfire Errata |
34 | * #51. Essentially, if a memory barrier occurs soon after a mispredicted | 36 | * #51. Essentially, if a memory barrier occurs soon after a mispredicted |
35 | * branch, the chip can stop executing instructions until a trap occurs. | 37 | * branch, the chip can stop executing instructions until a trap occurs. |