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authorDavid S. Miller <davem@sunset.davemloft.net>2007-05-29 05:22:14 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-05-29 05:52:15 -0400
commit7db35f31cbb8ca1dbaba03d74b7db79ace084358 (patch)
tree98dcbdb70d613ba6ddcf7c8bec03d79748342109 /include/asm-sparc64
parent2d9e2763c22a4ce41c3cc5f35366a51f1eba38dc (diff)
[SPARC64]: Fill holes in hypervisor APIs and fix KTSB registry.
Several interfaces were missing and others misnumbered or improperly documented. Also, make sure to check the return value when registering the kernel TSBs with the hypervisor. This helped to find the 4MB kernel TSB alignment bug fixed in a previous changeset. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64')
-rw-r--r--include/asm-sparc64/hypervisor.h640
1 files changed, 593 insertions, 47 deletions
diff --git a/include/asm-sparc64/hypervisor.h b/include/asm-sparc64/hypervisor.h
index 0a241c82fc7b..5cdb1ff04838 100644
--- a/include/asm-sparc64/hypervisor.h
+++ b/include/asm-sparc64/hypervisor.h
@@ -73,6 +73,8 @@
73#define HV_ENOTSUPPORTED 13 /* Function not supported */ 73#define HV_ENOTSUPPORTED 13 /* Function not supported */
74#define HV_ENOMAP 14 /* No mapping found */ 74#define HV_ENOMAP 14 /* No mapping found */
75#define HV_ETOOMANY 15 /* Too many items specified */ 75#define HV_ETOOMANY 15 /* Too many items specified */
76#define HV_ECHANNEL 16 /* Invalid LDC channel */
77#define HV_EBUSY 17 /* Resource busy */
76 78
77/* mach_exit() 79/* mach_exit()
78 * TRAP: HV_FAST_TRAP 80 * TRAP: HV_FAST_TRAP
@@ -95,6 +97,10 @@
95 */ 97 */
96#define HV_FAST_MACH_EXIT 0x00 98#define HV_FAST_MACH_EXIT 0x00
97 99
100#ifndef __ASSEMBLY__
101extern void sun4v_mach_exit(unsigned long exit_core);
102#endif
103
98/* Domain services. */ 104/* Domain services. */
99 105
100/* mach_desc() 106/* mach_desc()
@@ -121,11 +127,12 @@
121#define HV_FAST_MACH_DESC 0x01 127#define HV_FAST_MACH_DESC 0x01
122 128
123#ifndef __ASSEMBLY__ 129#ifndef __ASSEMBLY__
124extern unsigned long sun4v_mach_desc(unsigned long buffer_pa, unsigned long buf_len, 130extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
131 unsigned long buf_len,
125 unsigned long *real_buf_len); 132 unsigned long *real_buf_len);
126#endif 133#endif
127 134
128/* mach_exit() 135/* mach_sir()
129 * TRAP: HV_FAST_TRAP 136 * TRAP: HV_FAST_TRAP
130 * FUNCTION: HV_FAST_MACH_SIR 137 * FUNCTION: HV_FAST_MACH_SIR
131 * ERRORS: This service does not return. 138 * ERRORS: This service does not return.
@@ -140,59 +147,67 @@ extern unsigned long sun4v_mach_desc(unsigned long buffer_pa, unsigned long buf_
140 */ 147 */
141#define HV_FAST_MACH_SIR 0x02 148#define HV_FAST_MACH_SIR 0x02
142 149
143/* mach_set_soft_state() 150#ifndef __ASSEMBLY__
151extern void sun4v_mach_sir(void);
152#endif
153
154/* mach_set_watchdog()
144 * TRAP: HV_FAST_TRAP 155 * TRAP: HV_FAST_TRAP
145 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE 156 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
146 * ARG0: software state 157 * ARG0: timeout in milliseconds
147 * ARG1: software state description pointer
148 * RET0: status 158 * RET0: status
149 * ERRORS: EINVAL software state not valid or software state 159 * RET1: time remaining in milliseconds
150 * description is not NULL terminated
151 * ENORADDR software state description pointer is not a
152 * valid real address
153 * EBADALIGNED software state description is not correctly
154 * aligned
155 * 160 *
156 * This allows the guest to report it's soft state to the hypervisor. There 161 * A guest uses this API to set a watchdog timer. Once the gues has set
157 * are two primary components to this state. The first part states whether 162 * the timer, it must call the timer service again either to disable or
158 * the guest software is running or not. The second containts optional 163 * postpone the expiration. If the timer expires before being reset or
159 * details specific to the software. 164 * disabled, then the hypervisor take a platform specific action leading
165 * to guest termination within a bounded time period. The platform action
166 * may include recovery actions such as reporting the expiration to a
167 * Service Processor, and/or automatically restarting the gues.
160 * 168 *
161 * The software state argument is defined below in HV_SOFT_STATE_*, and 169 * The 'timeout' parameter is specified in milliseconds, however the
162 * indicates whether the guest is operating normally or in a transitional 170 * implementated granularity is given by the 'watchdog-resolution'
163 * state. 171 * property in the 'platform' node of the guest's machine description.
172 * The largest allowed timeout value is specified by the
173 * 'watchdog-max-timeout' property of the 'platform' node.
164 * 174 *
165 * The software state description argument is a real address of a data buffer 175 * If the 'timeout' argument is not zero, the watchdog timer is set to
166 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL 176 * expire after a minimum of 'timeout' milliseconds.
167 * terminated 7-bit ASCII string of up to 31 characters not including the 177 *
168 * NULL termination. 178 * If the 'timeout' argument is zero, the watchdog timer is disabled.
179 *
180 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
181 * property, the hypervisor leaves the watchdog timer state unchanged,
182 * and returns a status of EINVAL.
183 *
184 * The 'time remaining' return value is valid regardless of whether the
185 * return status is EOK or EINVAL. A non-zero return value indicates the
186 * number of milliseconds that were remaining until the timer was to expire.
187 * If less than one millisecond remains, the return value is '1'. If the
188 * watchdog timer was disabled at the time of the call, the return value is
189 * zero.
190 *
191 * If the hypervisor cannot support the exact timeout value requested, but
192 * can support a larger timeout value, the hypervisor may round the actual
193 * timeout to a value larger than the requested timeout, consequently the
194 * 'time remaining' return value may be larger than the previously requested
195 * timeout value.
196 *
197 * Any guest OS debugger should be aware that the watchdog service may be in
198 * use. Consequently, it is recommended that the watchdog service is
199 * disabled upon debugger entry (e.g. reaching a breakpoint), and then
200 * re-enabled upon returning to normal execution. The API has been designed
201 * with this in mind, and the 'time remaining' result of the disable call may
202 * be used directly as the timeout argument of the re-enable call.
169 */ 203 */
170#define HV_FAST_MACH_SET_SOFT_STATE 0x70 204#define HV_FAST_MACH_SET_WATCHDOG 0x05
171#define HV_SOFT_STATE_NORMAL 0x01
172#define HV_SOFT_STATE_TRANSITION 0x02
173 205
174#ifndef __ASSEMBLY__ 206#ifndef __ASSEMBLY__
175extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state, 207extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
176 unsigned long msg_string_ra); 208 unsigned long *orig_timeout);
177#endif 209#endif
178 210
179/* mach_get_soft_state()
180 * TRAP: HV_FAST_TRAP
181 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
182 * ARG0: software state description pointer
183 * RET0: status
184 * RET1: software state
185 * ERRORS: ENORADDR software state description pointer is not a
186 * valid real address
187 * EBADALIGNED software state description is not correctly
188 * aligned
189 *
190 * Retrieve the current value of the guest's software state. The rules
191 * for the software state pointer are the same as for mach_set_soft_state()
192 * above.
193 */
194#define HV_FAST_MACH_GET_SOFT_STATE 0x71
195
196/* CPU services. 211/* CPU services.
197 * 212 *
198 * CPUs represent devices that can execute software threads. A single 213 * CPUs represent devices that can execute software threads. A single
@@ -216,8 +231,8 @@ extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
216 * FUNCTION: HV_FAST_CPU_START 231 * FUNCTION: HV_FAST_CPU_START
217 * ARG0: CPU ID 232 * ARG0: CPU ID
218 * ARG1: PC 233 * ARG1: PC
219 * ARG1: RTBA 234 * ARG2: RTBA
220 * ARG1: target ARG0 235 * ARG3: target ARG0
221 * RET0: status 236 * RET0: status
222 * ERRORS: ENOCPU Invalid CPU ID 237 * ERRORS: ENOCPU Invalid CPU ID
223 * EINVAL Target CPU ID is not in the stopped state 238 * EINVAL Target CPU ID is not in the stopped state
@@ -234,6 +249,13 @@ extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
234 */ 249 */
235#define HV_FAST_CPU_START 0x10 250#define HV_FAST_CPU_START 0x10
236 251
252#ifndef __ASSEMBLY__
253extern unsigned long sun4v_cpu_start(unsigned long cpuid,
254 unsigned long pc,
255 unsigned long rtba,
256 unsigned long arg0);
257#endif
258
237/* cpu_stop() 259/* cpu_stop()
238 * TRAP: HV_FAST_TRAP 260 * TRAP: HV_FAST_TRAP
239 * FUNCTION: HV_FAST_CPU_STOP 261 * FUNCTION: HV_FAST_CPU_STOP
@@ -255,6 +277,10 @@ extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
255 */ 277 */
256#define HV_FAST_CPU_STOP 0x11 278#define HV_FAST_CPU_STOP 0x11
257 279
280#ifndef __ASSEMBLY__
281extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
282#endif
283
258/* cpu_yield() 284/* cpu_yield()
259 * TRAP: HV_FAST_TRAP 285 * TRAP: HV_FAST_TRAP
260 * FUNCTION: HV_FAST_CPU_YIELD 286 * FUNCTION: HV_FAST_CPU_YIELD
@@ -598,6 +624,11 @@ struct hv_fault_status {
598 */ 624 */
599#define HV_FAST_MMU_TSB_CTX0 0x20 625#define HV_FAST_MMU_TSB_CTX0 0x20
600 626
627#ifndef __ASSEMBLY__
628extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
629 unsigned long tsb_desc_ra);
630#endif
631
601/* mmu_tsb_ctxnon0() 632/* mmu_tsb_ctxnon0()
602 * TRAP: HV_FAST_TRAP 633 * TRAP: HV_FAST_TRAP
603 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0 634 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
@@ -704,6 +735,13 @@ struct hv_fault_status {
704 */ 735 */
705#define HV_FAST_MMU_MAP_PERM_ADDR 0x25 736#define HV_FAST_MMU_MAP_PERM_ADDR 0x25
706 737
738#ifndef __ASSEMBLY__
739extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
740 unsigned long set_to_zero,
741 unsigned long tte,
742 unsigned long flags);
743#endif
744
707/* mmu_fault_area_conf() 745/* mmu_fault_area_conf()
708 * TRAP: HV_FAST_TRAP 746 * TRAP: HV_FAST_TRAP
709 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF 747 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
@@ -902,6 +940,10 @@ struct hv_fault_status {
902 */ 940 */
903#define HV_FAST_TOD_GET 0x50 941#define HV_FAST_TOD_GET 0x50
904 942
943#ifndef __ASSEMBLY__
944extern unsigned long sun4v_tod_get(unsigned long *time);
945#endif
946
905/* tod_set() 947/* tod_set()
906 * TRAP: HV_FAST_TRAP 948 * TRAP: HV_FAST_TRAP
907 * FUNCTION: HV_FAST_TOD_SET 949 * FUNCTION: HV_FAST_TOD_SET
@@ -915,6 +957,10 @@ struct hv_fault_status {
915 */ 957 */
916#define HV_FAST_TOD_SET 0x51 958#define HV_FAST_TOD_SET 0x51
917 959
960#ifndef __ASSEMBLY__
961extern unsigned long sun4v_tod_set(unsigned long time);
962#endif
963
918/* Console services */ 964/* Console services */
919 965
920/* con_getchar() 966/* con_getchar()
@@ -998,6 +1044,59 @@ extern unsigned long sun4v_con_write(unsigned long buffer,
998 unsigned long *bytes_written); 1044 unsigned long *bytes_written);
999#endif 1045#endif
1000 1046
1047/* mach_set_soft_state()
1048 * TRAP: HV_FAST_TRAP
1049 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
1050 * ARG0: software state
1051 * ARG1: software state description pointer
1052 * RET0: status
1053 * ERRORS: EINVAL software state not valid or software state
1054 * description is not NULL terminated
1055 * ENORADDR software state description pointer is not a
1056 * valid real address
1057 * EBADALIGNED software state description is not correctly
1058 * aligned
1059 *
1060 * This allows the guest to report it's soft state to the hypervisor. There
1061 * are two primary components to this state. The first part states whether
1062 * the guest software is running or not. The second containts optional
1063 * details specific to the software.
1064 *
1065 * The software state argument is defined below in HV_SOFT_STATE_*, and
1066 * indicates whether the guest is operating normally or in a transitional
1067 * state.
1068 *
1069 * The software state description argument is a real address of a data buffer
1070 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
1071 * terminated 7-bit ASCII string of up to 31 characters not including the
1072 * NULL termination.
1073 */
1074#define HV_FAST_MACH_SET_SOFT_STATE 0x70
1075#define HV_SOFT_STATE_NORMAL 0x01
1076#define HV_SOFT_STATE_TRANSITION 0x02
1077
1078#ifndef __ASSEMBLY__
1079extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1080 unsigned long msg_string_ra);
1081#endif
1082
1083/* mach_get_soft_state()
1084 * TRAP: HV_FAST_TRAP
1085 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
1086 * ARG0: software state description pointer
1087 * RET0: status
1088 * RET1: software state
1089 * ERRORS: ENORADDR software state description pointer is not a
1090 * valid real address
1091 * EBADALIGNED software state description is not correctly
1092 * aligned
1093 *
1094 * Retrieve the current value of the guest's software state. The rules
1095 * for the software state pointer are the same as for mach_set_soft_state()
1096 * above.
1097 */
1098#define HV_FAST_MACH_GET_SOFT_STATE 0x71
1099
1001/* Trap trace services. 1100/* Trap trace services.
1002 * 1101 *
1003 * The hypervisor provides a trap tracing capability for privileged 1102 * The hypervisor provides a trap tracing capability for privileged
@@ -1389,6 +1488,113 @@ extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
1389extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid); 1488extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1390#endif 1489#endif
1391 1490
1491/* vintr_get_cookie()
1492 * TRAP: HV_FAST_TRAP
1493 * FUNCTION: HV_FAST_VINTR_GET_COOKIE
1494 * ARG0: device handle
1495 * ARG1: device ino
1496 * RET0: status
1497 * RET1: cookie
1498 */
1499#define HV_FAST_VINTR_GET_COOKIE 0xa7
1500
1501/* vintr_set_cookie()
1502 * TRAP: HV_FAST_TRAP
1503 * FUNCTION: HV_FAST_VINTR_SET_COOKIE
1504 * ARG0: device handle
1505 * ARG1: device ino
1506 * ARG2: cookie
1507 * RET0: status
1508 */
1509#define HV_FAST_VINTR_SET_COOKIE 0xa8
1510
1511/* vintr_get_valid()
1512 * TRAP: HV_FAST_TRAP
1513 * FUNCTION: HV_FAST_VINTR_GET_VALID
1514 * ARG0: device handle
1515 * ARG1: device ino
1516 * RET0: status
1517 * RET1: valid state
1518 */
1519#define HV_FAST_VINTR_GET_VALID 0xa9
1520
1521/* vintr_set_valid()
1522 * TRAP: HV_FAST_TRAP
1523 * FUNCTION: HV_FAST_VINTR_SET_VALID
1524 * ARG0: device handle
1525 * ARG1: device ino
1526 * ARG2: valid state
1527 * RET0: status
1528 */
1529#define HV_FAST_VINTR_SET_VALID 0xaa
1530
1531/* vintr_get_state()
1532 * TRAP: HV_FAST_TRAP
1533 * FUNCTION: HV_FAST_VINTR_GET_STATE
1534 * ARG0: device handle
1535 * ARG1: device ino
1536 * RET0: status
1537 * RET1: state
1538 */
1539#define HV_FAST_VINTR_GET_STATE 0xab
1540
1541/* vintr_set_state()
1542 * TRAP: HV_FAST_TRAP
1543 * FUNCTION: HV_FAST_VINTR_SET_STATE
1544 * ARG0: device handle
1545 * ARG1: device ino
1546 * ARG2: state
1547 * RET0: status
1548 */
1549#define HV_FAST_VINTR_SET_STATE 0xac
1550
1551/* vintr_get_target()
1552 * TRAP: HV_FAST_TRAP
1553 * FUNCTION: HV_FAST_VINTR_GET_TARGET
1554 * ARG0: device handle
1555 * ARG1: device ino
1556 * RET0: status
1557 * RET1: cpuid
1558 */
1559#define HV_FAST_VINTR_GET_TARGET 0xad
1560
1561/* vintr_set_target()
1562 * TRAP: HV_FAST_TRAP
1563 * FUNCTION: HV_FAST_VINTR_SET_TARGET
1564 * ARG0: device handle
1565 * ARG1: device ino
1566 * ARG2: cpuid
1567 * RET0: status
1568 */
1569#define HV_FAST_VINTR_SET_TARGET 0xae
1570
1571#ifndef __ASSEMBLY__
1572extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1573 unsigned long dev_ino,
1574 unsigned long *cookie);
1575extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1576 unsigned long dev_ino,
1577 unsigned long cookie);
1578extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1579 unsigned long dev_ino,
1580 unsigned long *valid);
1581extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1582 unsigned long dev_ino,
1583 unsigned long valid);
1584extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1585 unsigned long dev_ino,
1586 unsigned long *state);
1587extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1588 unsigned long dev_ino,
1589 unsigned long state);
1590extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1591 unsigned long dev_ino,
1592 unsigned long *cpuid);
1593extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1594 unsigned long dev_ino,
1595 unsigned long cpuid);
1596#endif
1597
1392/* PCI IO services. 1598/* PCI IO services.
1393 * 1599 *
1394 * See the terminology descriptions in the device interrupt services 1600 * See the terminology descriptions in the device interrupt services
@@ -2047,6 +2253,346 @@ extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cp
2047 */ 2253 */
2048#define HV_FAST_PCI_MSG_SETVALID 0xd3 2254#define HV_FAST_PCI_MSG_SETVALID 0xd3
2049 2255
2256/* Logical Domain Channel services. */
2257
2258#define LDC_CHANNEL_DOWN 0
2259#define LDC_CHANNEL_UP 1
2260#define LDC_CHANNEL_RESETTING 2
2261
2262/* ldc_tx_qconf()
2263 * TRAP: HV_FAST_TRAP
2264 * FUNCTION: HV_FAST_LDC_TX_QCONF
2265 * ARG0: channel ID
2266 * ARG1: real address base of queue
2267 * ARG2: num entries in queue
2268 * RET0: status
2269 *
2270 * Configure transmit queue for the LDC endpoint specified by the
2271 * given channel ID, to be placed at the given real address, and
2272 * be of the given num entries. Num entries must be a power of two.
2273 * The real address base of the queue must be aligned on the queue
2274 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2275 * queue must be aligned on a 2048 byte real address boundary.
2276 *
2277 * Upon configuration of a valid transmit queue the head and tail
2278 * pointers are set to a hypervisor specific identical value indicating
2279 * that the queue initially is empty.
2280 *
2281 * The endpoint's transmit queue is un-configured if num entries is zero.
2282 *
2283 * The maximum number of entries for each queue for a specific cpu may be
2284 * determined from the machine description. A transmit queue may be
2285 * specified even in the event that the LDC is down (peer endpoint has no
2286 * receive queue specified). Transmission will begin as soon as the peer
2287 * endpoint defines a receive queue.
2288 *
2289 * It is recommended that a guest wait for a transmit queue to empty prior
2290 * to reconfiguring it, or un-configuring it. Re or un-configuring of a
2291 * non-empty transmit queue behaves exactly as defined above, however it
2292 * is undefined as to how many of the pending entries in the original queue
2293 * will be delivered prior to the re-configuration taking effect.
2294 * Furthermore, as the queue configuration causes a reset of the head and
2295 * tail pointers there is no way for a guest to determine how many entries
2296 * have been sent after the configuration operation.
2297 */
2298#define HV_FAST_LDC_TX_QCONF 0xe0
2299
2300/* ldc_tx_qinfo()
2301 * TRAP: HV_FAST_TRAP
2302 * FUNCTION: HV_FAST_LDC_TX_QINFO
2303 * ARG0: channel ID
2304 * RET0: status
2305 * RET1: real address base of queue
2306 * RET2: num entries in queue
2307 *
2308 * Return the configuration info for the transmit queue of LDC endpoint
2309 * defined by the given channel ID. The real address is the currently
2310 * defined real address base of the defined queue, and num entries is the
2311 * size of the queue in terms of number of entries.
2312 *
2313 * If the specified channel ID is a valid endpoint number, but no transmit
2314 * queue has been defined this service will return success, but with num
2315 * entries set to zero and the real address will have an undefined value.
2316 */
2317#define HV_FAST_LDC_TX_QINFO 0xe1
2318
2319/* ldc_tx_get_state()
2320 * TRAP: HV_FAST_TRAP
2321 * FUNCTION: HV_FAST_LDC_TX_GET_STATE
2322 * ARG0: channel ID
2323 * RET0: status
2324 * RET1: head offset
2325 * RET2: tail offset
2326 * RET3: channel state
2327 *
2328 * Return the transmit state, and the head and tail queue pointers, for
2329 * the transmit queue of the LDC endpoint defined by the given channel ID.
2330 * The head and tail values are the byte offset of the head and tail
2331 * positions of the transmit queue for the specified endpoint.
2332 */
2333#define HV_FAST_LDC_TX_GET_STATE 0xe2
2334
2335/* ldc_tx_set_qtail()
2336 * TRAP: HV_FAST_TRAP
2337 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
2338 * ARG0: channel ID
2339 * ARG1: tail offset
2340 * RET0: status
2341 *
2342 * Update the tail pointer for the transmit queue associated with the LDC
2343 * endpoint defined by the given channel ID. The tail offset specified
2344 * must be aligned on a 64 byte boundary, and calculated so as to increase
2345 * the number of pending entries on the transmit queue. Any attempt to
2346 * decrease the number of pending transmit queue entires is considered
2347 * an invalid tail offset and will result in an EINVAL error.
2348 *
2349 * Since the tail of the transmit queue may not be moved backwards, the
2350 * transmit queue may be flushed by configuring a new transmit queue,
2351 * whereupon the hypervisor will configure the initial transmit head and
2352 * tail pointers to be equal.
2353 */
2354#define HV_FAST_LDC_TX_SET_QTAIL 0xe3
2355
2356/* ldc_rx_qconf()
2357 * TRAP: HV_FAST_TRAP
2358 * FUNCTION: HV_FAST_LDC_RX_QCONF
2359 * ARG0: channel ID
2360 * ARG1: real address base of queue
2361 * ARG2: num entries in queue
2362 * RET0: status
2363 *
2364 * Configure receive queue for the LDC endpoint specified by the
2365 * given channel ID, to be placed at the given real address, and
2366 * be of the given num entries. Num entries must be a power of two.
2367 * The real address base of the queue must be aligned on the queue
2368 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2369 * queue must be aligned on a 2048 byte real address boundary.
2370 *
2371 * The endpoint's transmit queue is un-configured if num entries is zero.
2372 *
2373 * If a valid receive queue is specified for a local endpoint the LDC is
2374 * in the up state for the purpose of transmission to this endpoint.
2375 *
2376 * The maximum number of entries for each queue for a specific cpu may be
2377 * determined from the machine description.
2378 *
2379 * As receive queue configuration causes a reset of the queue's head and
2380 * tail pointers there is no way for a gues to determine how many entries
2381 * have been received between a preceeding ldc_get_rx_state() API call
2382 * and the completion of the configuration operation. It should be noted
2383 * that datagram delivery is not guarenteed via domain channels anyway,
2384 * and therefore any higher protocol should be resilient to datagram
2385 * loss if necessary. However, to overcome this specific race potential
2386 * it is recommended, for example, that a higher level protocol be employed
2387 * to ensure either retransmission, or ensure that no datagrams are pending
2388 * on the peer endpoint's transmit queue prior to the configuration process.
2389 */
2390#define HV_FAST_LDC_RX_QCONF 0xe4
2391
2392/* ldc_rx_qinfo()
2393 * TRAP: HV_FAST_TRAP
2394 * FUNCTION: HV_FAST_LDC_RX_QINFO
2395 * ARG0: channel ID
2396 * RET0: status
2397 * RET1: real address base of queue
2398 * RET2: num entries in queue
2399 *
2400 * Return the configuration info for the receive queue of LDC endpoint
2401 * defined by the given channel ID. The real address is the currently
2402 * defined real address base of the defined queue, and num entries is the
2403 * size of the queue in terms of number of entries.
2404 *
2405 * If the specified channel ID is a valid endpoint number, but no receive
2406 * queue has been defined this service will return success, but with num
2407 * entries set to zero and the real address will have an undefined value.
2408 */
2409#define HV_FAST_LDC_RX_QINFO 0xe5
2410
2411/* ldc_rx_get_state()
2412 * TRAP: HV_FAST_TRAP
2413 * FUNCTION: HV_FAST_LDC_RX_GET_STATE
2414 * ARG0: channel ID
2415 * RET0: status
2416 * RET1: head offset
2417 * RET2: tail offset
2418 * RET3: channel state
2419 *
2420 * Return the receive state, and the head and tail queue pointers, for
2421 * the receive queue of the LDC endpoint defined by the given channel ID.
2422 * The head and tail values are the byte offset of the head and tail
2423 * positions of the receive queue for the specified endpoint.
2424 */
2425#define HV_FAST_LDC_RX_GET_STATE 0xe6
2426
2427/* ldc_rx_set_qhead()
2428 * TRAP: HV_FAST_TRAP
2429 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
2430 * ARG0: channel ID
2431 * ARG1: head offset
2432 * RET0: status
2433 *
2434 * Update the head pointer for the receive queue associated with the LDC
2435 * endpoint defined by the given channel ID. The head offset specified
2436 * must be aligned on a 64 byte boundary, and calculated so as to decrease
2437 * the number of pending entries on the receive queue. Any attempt to
2438 * increase the number of pending receive queue entires is considered
2439 * an invalid head offset and will result in an EINVAL error.
2440 *
2441 * The receive queue may be flushed by setting the head offset equal
2442 * to the current tail offset.
2443 */
2444#define HV_FAST_LDC_RX_SET_QHEAD 0xe7
2445
2446/* LDC Map Table Entry. Each slot is defined by a translation table
2447 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
2448 * hypervisor invalidation cookie.
2449 */
2450#define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
2451#define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
2452#define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
2453#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
2454#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
2455#define LDC_MTE_EXEC 0x0000000000000040 /* execute */
2456#define LDC_MTE_WRITE 0x0000000000000020 /* read */
2457#define LDC_MTE_READ 0x0000000000000010 /* write */
2458#define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
2459#define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
2460#define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
2461#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
2462#define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
2463#define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
2464#define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
2465#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
2466#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
2467
2468#ifndef __ASSEMBLY__
2469struct ldc_mtable_entry {
2470 unsigned long mte;
2471 unsigned long cookie;
2472};
2473#endif
2474
2475/* ldc_set_map_table()
2476 * TRAP: HV_FAST_TRAP
2477 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
2478 * ARG0: channel ID
2479 * ARG1: table real address
2480 * ARG2: num entries
2481 * RET0: status
2482 *
2483 * Register the MTE table at the given table real address, with the
2484 * specified num entries, for the LDC indicated by the given channel
2485 * ID.
2486 */
2487#define HV_FAST_LDC_SET_MAP_TABLE 0xea
2488
2489/* ldc_get_map_table()
2490 * TRAP: HV_FAST_TRAP
2491 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
2492 * ARG0: channel ID
2493 * RET0: status
2494 * RET1: table real address
2495 * RET2: num entries
2496 *
2497 * Return the configuration of the current mapping table registered
2498 * for the given channel ID.
2499 */
2500#define HV_FAST_LDC_GET_MAP_TABLE 0xeb
2501
2502#define LDC_COPY_IN 0
2503#define LDC_COPY_OUT 1
2504
2505/* ldc_copy()
2506 * TRAP: HV_FAST_TRAP
2507 * FUNCTION: HV_FAST_LDC_COPY
2508 * ARG0: channel ID
2509 * ARG1: LDC_COPY_* direction code
2510 * ARG2: target real address
2511 * ARG3: local real address
2512 * ARG4: length in bytes
2513 * RET0: status
2514 * RET1: actual length in bytes
2515 */
2516#define HV_FAST_LDC_COPY 0xec
2517
2518#define LDC_MEM_READ 1
2519#define LDC_MEM_WRITE 2
2520#define LDC_MEM_EXEC 4
2521
2522/* ldc_mapin()
2523 * TRAP: HV_FAST_TRAP
2524 * FUNCTION: HV_FAST_LDC_MAPIN
2525 * ARG0: channel ID
2526 * ARG1: cookie
2527 * RET0: status
2528 * RET1: real address
2529 * RET2: LDC_MEM_* permissions
2530 */
2531#define HV_FAST_LDC_MAPIN 0xed
2532
2533/* ldc_unmap()
2534 * TRAP: HV_FAST_TRAP
2535 * FUNCTION: HV_FAST_LDC_UNMAP
2536 * ARG0: real address
2537 * RET0: status
2538 */
2539#define HV_FAST_LDC_UNMAP 0xee
2540
2541/* ldc_revoke()
2542 * TRAP: HV_FAST_TRAP
2543 * FUNCTION: HV_FAST_LDC_REVOKE
2544 * ARG0: cookie
2545 * ARG1: ldc_mtable_entry cookie
2546 * RET0: status
2547 */
2548#define HV_FAST_LDC_REVOKE 0xef
2549
2550#ifndef __ASSEMBLY__
2551extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
2552 unsigned long ra,
2553 unsigned long num_entries);
2554extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
2555 unsigned long *ra,
2556 unsigned long *num_entries);
2557extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
2558 unsigned long *head_off,
2559 unsigned long *tail_off,
2560 unsigned long *chan_state);
2561extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
2562 unsigned long tail_off);
2563extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
2564 unsigned long ra,
2565 unsigned long num_entries);
2566extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
2567 unsigned long *ra,
2568 unsigned long *num_entries);
2569extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
2570 unsigned long *head_off,
2571 unsigned long *tail_off,
2572 unsigned long *chan_state);
2573extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
2574 unsigned long head_off);
2575extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
2576 unsigned long ra,
2577 unsigned long num_entries);
2578extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
2579 unsigned long *ra,
2580 unsigned long *num_entries);
2581extern unsigned long sun4v_ldc_copy(unsigned long channel,
2582 unsigned long dir_code,
2583 unsigned long tgt_raddr,
2584 unsigned long lcl_raddr,
2585 unsigned long len,
2586 unsigned long *actual_len);
2587extern unsigned long sun4v_ldc_mapin(unsigned long channel,
2588 unsigned long cookie,
2589 unsigned long *ra,
2590 unsigned long *perm);
2591extern unsigned long sun4v_ldc_unmap(unsigned long ra);
2592extern unsigned long sun4v_ldc_revoke(unsigned long cookie,
2593 unsigned long mte_cookie);
2594#endif
2595
2050/* Performance counter services. */ 2596/* Performance counter services. */
2051 2597
2052#define HV_PERF_JBUS_PERF_CTRL_REG 0x00 2598#define HV_PERF_JBUS_PERF_CTRL_REG 0x00