[SPARC64]: Add irqtrace/stacktrace/lockdep support.

Signed-off-by: David S. Miller <davem@davemloft.net>

4 files changed, 160 insertions, 55 deletions

diff --git a/include/asm-sparc64/irqflags.h b/include/asm-sparc64/irqflags.h
new file mode 100644
index 000000000000..024fc54d0682
--- /dev/null
+++ b/include/asm-sparc64/irqflags.h
@@ -0,0 +1,89 @@
+/*
+ * include/asm-sparc64/irqflags.h
+ *
+ * IRQ flags handling
+ *
+ * This file gets included from lowlevel asm headers too, to provide
+ * wrapped versions of the local_irq_*() APIs, based on the
+ * raw_local_irq_*() functions from the lowlevel headers.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__(
+                "rdpr   %%pil, %0"
+                : "=r" (flags)
+        );
+
+        return flags;
+}
+
+#define raw_local_save_flags(flags) \
+                do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        __asm__ __volatile__(
+                "wrpr   %0, %%pil"
+                : /* no output */
+                : "r" (flags)
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+        __asm__ __volatile__(
+                "wrpr   15, %%pil"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_enable(void)
+{
+        __asm__ __volatile__(
+                "wrpr   0, %%pil"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags > 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        return raw_irqs_disabled_flags(flags);
+}
+
+/*
+ * For spinlocks, etc:
+ */
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        raw_local_irq_disable();
+
+        return flags;
+}
+
+#define raw_local_irq_save(flags) \
+                do { (flags) = __raw_local_irq_save(); } while (0)
+
+#endif /* (__ASSEMBLY__) */
+
+#endif /* !(_ASM_IRQFLAGS_H) */
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index cef5e8270421..1294b7ce5d06 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -23,20 +23,33 @@ struct rw_semaphore {
         signed int count;
         spinlock_t              wait_lock;
         struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
 };
 
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
 #define __RWSEM_INITIALIZER(name) \
-{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) }
+{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
+  __RWSEM_DEP_MAP_INIT(name) }
 
 #define DECLARE_RWSEM(name) \
         struct rw_semaphore name = __RWSEM_INITIALIZER(name)
 
-static __inline__ void init_rwsem(struct rw_semaphore *sem)
-{
-        sem->count = RWSEM_UNLOCKED_VALUE;
-        spin_lock_init(&sem->wait_lock);
-        INIT_LIST_HEAD(&sem->wait_list);
-}
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                                         \
+do {                                                            \
+        static struct lock_class_key __key;                     \
+                                                                \
+        __init_rwsem((sem), #sem, &__key);                      \
+} while (0)
 
 extern void __down_read(struct rw_semaphore *sem);
 extern int __down_read_trylock(struct rw_semaphore *sem);
@@ -46,6 +59,11 @@ extern void __up_read(struct rw_semaphore *sem);
 extern void __up_write(struct rw_semaphore *sem);
 extern void __downgrade_write(struct rw_semaphore *sem);
 
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        __down_write(sem);
+}
+
 static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
 {
         return atomic_add_return(delta, (atomic_t *)(&sem->count));
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index a8b7432c9a70..32281acb878b 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -7,6 +7,9 @@
 #include <asm/visasm.h>
 
 #ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+
 /*
  * Sparc (general) CPU types
  */
@@ -72,52 +75,6 @@ do {	__asm__ __volatile__("ba,pt	%%xcc, 1f\n\t" \
 
 #endif
 
-#define setipl(__new_ipl) \
-        __asm__ __volatile__("wrpr      %0, %%pil"  : : "r" (__new_ipl) : "memory")
-
-#define local_irq_disable() \
-        __asm__ __volatile__("wrpr      15, %%pil" : : : "memory")
-
-#define local_irq_enable() \
-        __asm__ __volatile__("wrpr      0, %%pil" : : : "memory")
-
-#define getipl() \
-({ unsigned long retval; __asm__ __volatile__("rdpr     %%pil, %0" : "=r" (retval)); retval; })
-
-#define swap_pil(__new_pil) \
-({      unsigned long retval; \
-        __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
-                             "wrpr      %1, %%pil" \
-                             : "=&r" (retval) \
-                             : "r" (__new_pil) \
-                             : "memory"); \
-        retval; \
-})
-
-#define read_pil_and_cli() \
-({      unsigned long retval; \
-        __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
-                             "wrpr      15, %%pil" \
-                             : "=r" (retval) \
-                             : : "memory"); \
-        retval; \
-})
-
-#define local_save_flags(flags)         ((flags) = getipl())
-#define local_irq_save(flags)           ((flags) = read_pil_and_cli())
-#define local_irq_restore(flags)                setipl((flags))
-
-/* On sparc64 IRQ flags are the PIL register.  A value of zero
- * means all interrupt levels are enabled, any other value means
- * only IRQ levels greater than that value will be received.
- * Consequently this means that the lowest IRQ level is one.
- */
-#define irqs_disabled()         \
-({      unsigned long flags;    \
-        local_save_flags(flags);\
-        (flags > 0);            \
-})
-
 #define nop()           __asm__ __volatile__ ("nop")
 
 #define read_barrier_depends()          do { } while(0)
diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h
index f2352606a79f..c2a16e188499 100644
--- a/include/asm-sparc64/ttable.h
+++ b/include/asm-sparc64/ttable.h
@@ -137,10 +137,49 @@
 #endif
 #define BREAKPOINT_TRAP TRAP(breakpoint_trap)
 
+#ifdef CONFIG_TRACE_IRQFLAGS
+
+#define TRAP_IRQ(routine, level)                        \
+        rdpr    %pil, %g2;                              \
+        wrpr    %g0, 15, %pil;                          \
+        sethi   %hi(1f-4), %g7;                         \
+        ba,pt   %xcc, etrap_irq;                        \
+         or     %g7, %lo(1f-4), %g7;                    \
+        nop;                                            \
+        nop;                                            \
+        nop;                                            \
+        .subsection     2;                              \
+1:      call    trace_hardirqs_off;                     \
+         nop;                                           \
+        mov     level, %o0;                             \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o1;                   \
+        ba,a,pt %xcc, rtrap_irq;                        \
+        .previous;
+
+#define TICK_SMP_IRQ                                    \
+        rdpr    %pil, %g2;                              \
+        wrpr    %g0, 15, %pil;                          \
+        sethi   %hi(1f-4), %g7;                         \
+        ba,pt   %xcc, etrap_irq;                        \
+         or     %g7, %lo(1f-4), %g7;                    \
+        nop;                                            \
+        nop;                                            \
+        nop;                                            \
+        .subsection     2;                              \
+1:      call    trace_hardirqs_off;                     \
+         nop;                                           \
+        call    smp_percpu_timer_interrupt;             \
+         add    %sp, PTREGS_OFF, %o0;                   \
+        ba,a,pt %xcc, rtrap_irq;                        \
+        .previous;
+
+#else
+
 #define TRAP_IRQ(routine, level)                        \
         rdpr    %pil, %g2;                              \
         wrpr    %g0, 15, %pil;                          \
-        b,pt    %xcc, etrap_irq;                        \
+        ba,pt   %xcc, etrap_irq;                        \
          rd     %pc, %g7;                               \
         mov     level, %o0;                             \
         call    routine;                                \
@@ -151,12 +190,14 @@
         rdpr    %pil, %g2;                              \
         wrpr    %g0, 15, %pil;                          \
         sethi   %hi(109f), %g7;                         \
-        b,pt    %xcc, etrap_irq;                        \
+        ba,pt   %xcc, etrap_irq;                        \
 109:     or     %g7, %lo(109b), %g7;                    \
         call    smp_percpu_timer_interrupt;             \
          add    %sp, PTREGS_OFF, %o0;                   \
         ba,a,pt %xcc, rtrap_irq;
 
+#endif
+
 #define TRAP_IVEC TRAP_NOSAVE(do_ivec)
 
 #define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)