diff options
author | David S. Miller <davem@davemloft.net> | 2005-09-08 17:37:53 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2005-09-08 17:37:53 -0400 |
commit | 4d803fcdcd97dd346d4b39c3b76e5879cead8a31 (patch) | |
tree | f30c8caa998261fc0983121021184f0f6cc555b4 /include/asm-sparc64 | |
parent | 1b11d78cf87a7014f96e5b7fa2e1233cc8081a00 (diff) |
[SPARC64]: Inline membar()'s again.
Since GCC has to emit a call and a delay slot to the
out-of-line "membar" routines in arch/sparc64/lib/mb.S
it is much better to just do the necessary predicted
branch inline instead as:
ba,pt %xcc, 1f
membar #whatever
1:
instead of the current:
call membar_foo
dslot
because this way GCC is not required to allocate a stack
frame if the function can be a leaf function.
This also makes this bug fix easier to backport to 2.4.x
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64')
-rw-r--r-- | include/asm-sparc64/system.h | 49 |
1 files changed, 42 insertions, 7 deletions
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h index 5e94c05dc2fc..b5417529f6f1 100644 --- a/include/asm-sparc64/system.h +++ b/include/asm-sparc64/system.h | |||
@@ -28,13 +28,48 @@ enum sparc_cpu { | |||
28 | #define ARCH_SUN4C_SUN4 0 | 28 | #define ARCH_SUN4C_SUN4 0 |
29 | #define ARCH_SUN4 0 | 29 | #define ARCH_SUN4 0 |
30 | 30 | ||
31 | extern void mb(void); | 31 | /* These are here in an effort to more fully work around Spitfire Errata |
32 | extern void rmb(void); | 32 | * #51. Essentially, if a memory barrier occurs soon after a mispredicted |
33 | extern void wmb(void); | 33 | * branch, the chip can stop executing instructions until a trap occurs. |
34 | extern void membar_storeload(void); | 34 | * Therefore, if interrupts are disabled, the chip can hang forever. |
35 | extern void membar_storeload_storestore(void); | 35 | * |
36 | extern void membar_storeload_loadload(void); | 36 | * It used to be believed that the memory barrier had to be right in the |
37 | extern void membar_storestore_loadstore(void); | 37 | * delay slot, but a case has been traced recently wherein the memory barrier |
38 | * was one instruction after the branch delay slot and the chip still hung. | ||
39 | * The offending sequence was the following in sym_wakeup_done() of the | ||
40 | * sym53c8xx_2 driver: | ||
41 | * | ||
42 | * call sym_ccb_from_dsa, 0 | ||
43 | * movge %icc, 0, %l0 | ||
44 | * brz,pn %o0, .LL1303 | ||
45 | * mov %o0, %l2 | ||
46 | * membar #LoadLoad | ||
47 | * | ||
48 | * The branch has to be mispredicted for the bug to occur. Therefore, we put | ||
49 | * the memory barrier explicitly into a "branch always, predicted taken" | ||
50 | * delay slot to avoid the problem case. | ||
51 | */ | ||
52 | #define membar_safe(type) \ | ||
53 | do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ | ||
54 | " membar " type "\n" \ | ||
55 | "1:\n" \ | ||
56 | : : : "memory"); \ | ||
57 | } while (0) | ||
58 | |||
59 | #define mb() \ | ||
60 | membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad") | ||
61 | #define rmb() \ | ||
62 | membar_safe("#LoadLoad") | ||
63 | #define wmb() \ | ||
64 | membar_safe("#StoreStore") | ||
65 | #define membar_storeload() \ | ||
66 | membar_safe("#StoreLoad") | ||
67 | #define membar_storeload_storestore() \ | ||
68 | membar_safe("#StoreLoad | #StoreStore") | ||
69 | #define membar_storeload_loadload() \ | ||
70 | membar_safe("#StoreLoad | #LoadLoad") | ||
71 | #define membar_storestore_loadstore() \ | ||
72 | membar_safe("#StoreStore | #LoadStore") | ||
38 | 73 | ||
39 | #endif | 74 | #endif |
40 | 75 | ||