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authorSam Ravnborg <sam@ravnborg.org>2008-06-19 14:26:19 -0400
committerDavid S. Miller <davem@davemloft.net>2008-07-18 00:44:53 -0400
commita00736e936c2a1e9c36f22f6f3a69392eaab51f4 (patch)
tree4fd3d203dbc30d50a1b0c1acce2957e082a75173 /include/asm-sparc64
parentbdc3135ac99efd59de084a309751ec76887e62d8 (diff)
sparc: copy sparc64 specific files to asm-sparc
Used the following script to copy the files: cd include set -e SPARC64=`ls asm-sparc64` for FILE in ${SPARC64}; do if [ -f asm-sparc/$FILE ]; then echo $FILE exist in asm-sparc else git mv asm-sparc64/$FILE asm-sparc/$FILE printf "#include <asm-sparc/$FILE>\n" > asm-sparc64/$FILE git add asm-sparc64/$FILE fi done Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Diffstat (limited to 'include/asm-sparc64')
-rw-r--r--include/asm-sparc64/agp.h21
-rw-r--r--include/asm-sparc64/apb.h37
-rw-r--r--include/asm-sparc64/backoff.h32
-rw-r--r--include/asm-sparc64/bbc.h226
-rw-r--r--include/asm-sparc64/chafsr.h242
-rw-r--r--include/asm-sparc64/chmctrl.h184
-rw-r--r--include/asm-sparc64/cmt.h60
-rw-r--r--include/asm-sparc64/compat.h244
-rw-r--r--include/asm-sparc64/compat_signal.h30
-rw-r--r--include/asm-sparc64/dcr.h15
-rw-r--r--include/asm-sparc64/dcu.h28
-rw-r--r--include/asm-sparc64/estate.h50
-rw-r--r--include/asm-sparc64/fhc.h122
-rw-r--r--include/asm-sparc64/fpumacro.h34
-rw-r--r--include/asm-sparc64/hugetlb.h85
-rw-r--r--include/asm-sparc64/hvtramp.h38
-rw-r--r--include/asm-sparc64/hypervisor.h2946
-rw-r--r--include/asm-sparc64/intr_queue.h16
-rw-r--r--include/asm-sparc64/kprobes.h50
-rw-r--r--include/asm-sparc64/ldc.h139
-rw-r--r--include/asm-sparc64/lmb.h11
-rw-r--r--include/asm-sparc64/lsu.h20
-rw-r--r--include/asm-sparc64/mdesc.h79
-rw-r--r--include/asm-sparc64/mmzone.h18
-rw-r--r--include/asm-sparc64/ns87303.h119
-rw-r--r--include/asm-sparc64/parport.h247
-rw-r--r--include/asm-sparc64/pil.h22
-rw-r--r--include/asm-sparc64/reboot.h7
-rw-r--r--include/asm-sparc64/rwsem-const.h13
-rw-r--r--include/asm-sparc64/rwsem.h85
-rw-r--r--include/asm-sparc64/scratchpad.h15
-rw-r--r--include/asm-sparc64/seccomp.h22
-rw-r--r--include/asm-sparc64/sfafsr.h83
-rw-r--r--include/asm-sparc64/sparsemem.h13
-rw-r--r--include/asm-sparc64/spitfire.h343
-rw-r--r--include/asm-sparc64/sstate.h14
-rw-r--r--include/asm-sparc64/stacktrace.h7
-rw-r--r--include/asm-sparc64/starfire.h22
-rw-r--r--include/asm-sparc64/syscalls.h14
-rw-r--r--include/asm-sparc64/tsb.h284
-rw-r--r--include/asm-sparc64/ttable.h659
-rw-r--r--include/asm-sparc64/upa.h110
-rw-r--r--include/asm-sparc64/vio.h407
-rw-r--r--include/asm-sparc64/visasm.h63
44 files changed, 44 insertions, 7232 deletions
diff --git a/include/asm-sparc64/agp.h b/include/asm-sparc64/agp.h
index e9fcf0e781ea..eb8d4b3f5163 100644
--- a/include/asm-sparc64/agp.h
+++ b/include/asm-sparc64/agp.h
@@ -1,20 +1 @@
1#ifndef AGP_H #include <asm-sparc/agp.h>
2#define AGP_H 1
3
4/* dummy for now */
5
6#define map_page_into_agp(page)
7#define unmap_page_from_agp(page)
8#define flush_agp_cache() mb()
9
10/* Convert a physical address to an address suitable for the GART. */
11#define phys_to_gart(x) (x)
12#define gart_to_phys(x) (x)
13
14/* GATT allocation. Returns/accepts GATT kernel virtual address. */
15#define alloc_gatt_pages(order) \
16 ((char *)__get_free_pages(GFP_KERNEL, (order)))
17#define free_gatt_pages(table, order) \
18 free_pages((unsigned long)(table), (order))
19
20#endif
diff --git a/include/asm-sparc64/apb.h b/include/asm-sparc64/apb.h
index 8f3b57db810f..5e236ca6e492 100644
--- a/include/asm-sparc64/apb.h
+++ b/include/asm-sparc64/apb.h
@@ -1,36 +1 @@
1/* #include <asm-sparc/apb.h>
2 * apb.h: Advanced PCI Bridge Configuration Registers and Bits
3 *
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 */
6
7#ifndef _SPARC64_APB_H
8#define _SPARC64_APB_H
9
10#define APB_TICK_REGISTER 0xb0
11#define APB_INT_ACK 0xb8
12#define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0
13#define APB_DMA_ASFR 0xc8
14#define APB_DMA_AFAR 0xd0
15#define APB_PIO_TARGET_RETRY_LIMIT 0xd8
16#define APB_PIO_TARGET_LATENCY_TIMER 0xd9
17#define APB_DMA_TARGET_RETRY_LIMIT 0xda
18#define APB_DMA_TARGET_LATENCY_TIMER 0xdb
19#define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc
20#define APB_SECONDARY_CONTROL 0xdd
21#define APB_IO_ADDRESS_MAP 0xde
22#define APB_MEM_ADDRESS_MAP 0xdf
23
24#define APB_PCI_CONTROL_LOW 0xe0
25# define APB_PCI_CTL_LOW_ARB_PARK (1 << 21)
26# define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8)
27
28#define APB_PCI_CONTROL_HIGH 0xe4
29# define APB_PCI_CTL_HIGH_SERR (1 << 2)
30# define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0)
31
32#define APB_PIO_ASFR 0xe8
33#define APB_PIO_AFAR 0xf0
34#define APB_DIAG_REGISTER 0xf8
35
36#endif /* !(_SPARC64_APB_H) */
diff --git a/include/asm-sparc64/backoff.h b/include/asm-sparc64/backoff.h
index fa1fdf67e350..8ee26d947e0e 100644
--- a/include/asm-sparc64/backoff.h
+++ b/include/asm-sparc64/backoff.h
@@ -1,31 +1 @@
1#ifndef _SPARC64_BACKOFF_H #include <asm-sparc/backoff.h>
2#define _SPARC64_BACKOFF_H
3
4#define BACKOFF_LIMIT (4 * 1024)
5
6#ifdef CONFIG_SMP
7
8#define BACKOFF_SETUP(reg) \
9 mov 1, reg
10
11#define BACKOFF_SPIN(reg, tmp, label) \
12 mov reg, tmp; \
1388: brnz,pt tmp, 88b; \
14 sub tmp, 1, tmp; \
15 set BACKOFF_LIMIT, tmp; \
16 cmp reg, tmp; \
17 bg,pn %xcc, label; \
18 nop; \
19 ba,pt %xcc, label; \
20 sllx reg, 1, reg;
21
22#else
23
24#define BACKOFF_SETUP(reg)
25#define BACKOFF_SPIN(reg, tmp, label) \
26 ba,pt %xcc, label; \
27 nop;
28
29#endif
30
31#endif /* _SPARC64_BACKOFF_H */
diff --git a/include/asm-sparc64/bbc.h b/include/asm-sparc64/bbc.h
index 423a85800aae..06e8b6306514 100644
--- a/include/asm-sparc64/bbc.h
+++ b/include/asm-sparc64/bbc.h
@@ -1,225 +1 @@
1/* #include <asm-sparc/bbc.h>
2 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
3 * systems.
4 *
5 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
6 */
7
8#ifndef _SPARC64_BBC_H
9#define _SPARC64_BBC_H
10
11/* Register sizes are indicated by "B" (Byte, 1-byte),
12 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
13 * "Q" (Quad, 8 bytes) inside brackets.
14 */
15
16#define BBC_AID 0x00 /* [B] Agent ID */
17#define BBC_DEVP 0x01 /* [B] Device Present */
18#define BBC_ARB 0x02 /* [B] Arbitration */
19#define BBC_QUIESCE 0x03 /* [B] Quiesce */
20#define BBC_WDACTION 0x04 /* [B] Watchdog Action */
21#define BBC_SPG 0x06 /* [B] Soft POR Gen */
22#define BBC_SXG 0x07 /* [B] Soft XIR Gen */
23#define BBC_PSRC 0x08 /* [W] POR Source */
24#define BBC_XSRC 0x0c /* [B] XIR Source */
25#define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
26#define BBC_ES_CTRL 0x0e /* [H] Energy Star Control */
27#define BBC_ES_ACT 0x10 /* [W] E* Assert Change Time */
28#define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
29#define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
30#define BBC_ES_ABT 0x16 /* [H] E* Assert Bypass Time */
31#define BBC_ES_PST 0x18 /* [W] E* PLL Settle Time */
32#define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
33#define BBC_EBUST 0x20 /* [Q] EBUS Timing */
34#define BBC_JTAG_CMD 0x28 /* [W] JTAG+ Command */
35#define BBC_JTAG_CTRL 0x2c /* [B] JTAG+ Control */
36#define BBC_I2C_SEL 0x2d /* [B] I2C Selection */
37#define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
38#define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
39#define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
40#define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
41#define BBC_KBD_BEEP 0x32 /* [B] Keyboard Beep */
42#define BBC_KBD_BCNT 0x34 /* [W] Keyboard Beep Counter */
43
44#define BBC_REGS_SIZE 0x40
45
46/* There is a 2K scratch ram area at offset 0x80000 but I doubt
47 * we will use it for anything.
48 */
49
50/* Agent ID register. This register shows the Safari Agent ID
51 * for the processors. The value returned depends upon which
52 * cpu is reading the register.
53 */
54#define BBC_AID_ID 0x07 /* Safari ID */
55#define BBC_AID_RESV 0xf8 /* Reserved */
56
57/* Device Present register. One can determine which cpus are actually
58 * present in the machine by interrogating this register.
59 */
60#define BBC_DEVP_CPU0 0x01 /* Processor 0 present */
61#define BBC_DEVP_CPU1 0x02 /* Processor 1 present */
62#define BBC_DEVP_CPU2 0x04 /* Processor 2 present */
63#define BBC_DEVP_CPU3 0x08 /* Processor 3 present */
64#define BBC_DEVP_RESV 0xf0 /* Reserved */
65
66/* Arbitration register. This register is used to block access to
67 * the BBC from a particular cpu.
68 */
69#define BBC_ARB_CPU0 0x01 /* Enable cpu 0 BBC arbitratrion */
70#define BBC_ARB_CPU1 0x02 /* Enable cpu 1 BBC arbitratrion */
71#define BBC_ARB_CPU2 0x04 /* Enable cpu 2 BBC arbitratrion */
72#define BBC_ARB_CPU3 0x08 /* Enable cpu 3 BBC arbitratrion */
73#define BBC_ARB_RESV 0xf0 /* Reserved */
74
75/* Quiesce register. Bus and BBC segments for cpus can be disabled
76 * with this register, ie. for hot plugging.
77 */
78#define BBC_QUIESCE_S02 0x01 /* Quiesce Safari segment for cpu 0 and 2 */
79#define BBC_QUIESCE_S13 0x02 /* Quiesce Safari segment for cpu 1 and 3 */
80#define BBC_QUIESCE_B02 0x04 /* Quiesce BBC segment for cpu 0 and 2 */
81#define BBC_QUIESCE_B13 0x08 /* Quiesce BBC segment for cpu 1 and 3 */
82#define BBC_QUIESCE_FD0 0x10 /* Disable Fatal_Error[0] reporting */
83#define BBC_QUIESCE_FD1 0x20 /* Disable Fatal_Error[1] reporting */
84#define BBC_QUIESCE_FD2 0x40 /* Disable Fatal_Error[2] reporting */
85#define BBC_QUIESCE_FD3 0x80 /* Disable Fatal_Error[3] reporting */
86
87/* Watchdog Action register. When the watchdog device timer expires
88 * a line is enabled to the BBC. The action BBC takes when this line
89 * is asserted can be controlled by this regiser.
90 */
91#define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset.
92 * When clear, BBC ignores watchdog signal.
93 */
94#define BBC_WDACTION_RESV 0xfe /* Reserved */
95
96/* Soft_POR_GEN register. The POR (Power On Reset) signal may be asserted
97 * for specific processors or all processors via this register.
98 */
99#define BBC_SPG_CPU0 0x01 /* Assert POR for processor 0 */
100#define BBC_SPG_CPU1 0x02 /* Assert POR for processor 1 */
101#define BBC_SPG_CPU2 0x04 /* Assert POR for processor 2 */
102#define BBC_SPG_CPU3 0x08 /* Assert POR for processor 3 */
103#define BBC_SPG_CPUALL 0x10 /* Reset all processors and reset
104 * the entire system.
105 */
106#define BBC_SPG_RESV 0xe0 /* Reserved */
107
108/* Soft_XIR_GEN register. The XIR (eXternally Initiated Reset) signal
109 * may be asserted to specific processors via this register.
110 */
111#define BBC_SXG_CPU0 0x01 /* Assert XIR for processor 0 */
112#define BBC_SXG_CPU1 0x02 /* Assert XIR for processor 1 */
113#define BBC_SXG_CPU2 0x04 /* Assert XIR for processor 2 */
114#define BBC_SXG_CPU3 0x08 /* Assert XIR for processor 3 */
115#define BBC_SXG_RESV 0xf0 /* Reserved */
116
117/* POR Source register. One may identify the cause of the most recent
118 * reset by reading this register.
119 */
120#define BBC_PSRC_SPG0 0x0001 /* CPU 0 reset via BBC_SPG register */
121#define BBC_PSRC_SPG1 0x0002 /* CPU 1 reset via BBC_SPG register */
122#define BBC_PSRC_SPG2 0x0004 /* CPU 2 reset via BBC_SPG register */
123#define BBC_PSRC_SPG3 0x0008 /* CPU 3 reset via BBC_SPG register */
124#define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */
125#define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */
126#define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */
127#define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */
128#define BBC_PSRC_FE0 0x0100 /* CPU 0 reported Fatal_Error */
129#define BBC_PSRC_FE1 0x0200 /* CPU 1 reported Fatal_Error */
130#define BBC_PSRC_FE2 0x0400 /* CPU 2 reported Fatal_Error */
131#define BBC_PSRC_FE3 0x0800 /* CPU 3 reported Fatal_Error */
132#define BBC_PSRC_FE4 0x1000 /* Schizo reported Fatal_Error */
133#define BBC_PSRC_FE5 0x2000 /* Safari device 5 reported Fatal_Error */
134#define BBC_PSRC_FE6 0x4000 /* CPMS reported Fatal_Error */
135#define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers
136 * were updated.
137 */
138#define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */
139#define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring
140 * device
141 */
142
143/* XIR Source register. The source of an XIR event sent to a processor may
144 * be determined via this register.
145 */
146#define BBC_XSRC_SXG0 0x01 /* CPU 0 received XIR via Soft_XIR_GEN reg */
147#define BBC_XSRC_SXG1 0x02 /* CPU 1 received XIR via Soft_XIR_GEN reg */
148#define BBC_XSRC_SXG2 0x04 /* CPU 2 received XIR via Soft_XIR_GEN reg */
149#define BBC_XSRC_SXG3 0x08 /* CPU 3 received XIR via Soft_XIR_GEN reg */
150#define BBC_XSRC_JTAG 0x10 /* All CPUs received XIR via JTAG+ */
151#define BBC_XSRC_W_OR_B 0x20 /* All CPUs received XIR either because:
152 * a) Super I/O watchdog fired, or
153 * b) XIR push button was activated
154 */
155#define BBC_XSRC_RESV 0xc0 /* Reserved */
156
157/* Clock Synthesizers Control register. This register provides the big-bang
158 * programming interface to the two clock synthesizers of the machine.
159 */
160#define BBC_CSC_SLOAD 0x01 /* Directly connected to S_LOAD pins */
161#define BBC_CSC_SDATA 0x02 /* Directly connected to S_DATA pins */
162#define BBC_CSC_SCLOCK 0x04 /* Directly connected to S_CLOCK pins */
163#define BBC_CSC_RESV 0x78 /* Reserved */
164#define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */
165
166/* Energy Star Control register. This register is used to generate the
167 * clock frequency change trigger to the main system devices (Schizo and
168 * the processors). The transition occurs when bits in this register
169 * go from 0 to 1, only one bit must be set at once else no action
170 * occurs. Basically the sequence of events is:
171 * a) Choose new frequency: full, 1/2 or 1/32
172 * b) Program this desired frequency into the cpus and Schizo.
173 * c) Set the same value in this register.
174 * d) 16 system clocks later, clear this register.
175 */
176#define BBC_ES_CTRL_1_1 0x01 /* Full frequency */
177#define BBC_ES_CTRL_1_2 0x02 /* 1/2 frequency */
178#define BBC_ES_CTRL_1_32 0x20 /* 1/32 frequency */
179#define BBC_ES_RESV 0xdc /* Reserved */
180
181/* Energy Star Assert Change Time register. This determines the number
182 * of BBC clock cycles (which is half the system frequency) between
183 * the detection of FREEZE_ACK being asserted and the assertion of
184 * the CLK_CHANGE_L[2:0] signals.
185 */
186#define BBC_ES_ACT_VAL 0xff
187
188/* Energy Star Assert Bypass Time register. This determines the number
189 * of BBC clock cycles (which is half the system frequency) between
190 * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
191 * the ESTAR_PLL_BYPASS signal.
192 */
193#define BBC_ES_ABT_VAL 0xffff
194
195/* Energy Star PLL Settle Time register. This determines the number of
196 * BBC clock cycles (which is half the system frequency) between the
197 * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
198 * signal.
199 */
200#define BBC_ES_PST_VAL 0xffffffff
201
202/* Energy Star Frequency Switch Latency register. This is the number of
203 * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
204 * edge of the Safari clock at the new frequency.
205 */
206#define BBC_ES_FSL_VAL 0xffffffff
207
208/* Keyboard Beep control register. This is a simple enabler for the audio
209 * beep sound.
210 */
211#define BBC_KBD_BEEP_ENABLE 0x01 /* Enable beep */
212#define BBC_KBD_BEEP_RESV 0xfe /* Reserved */
213
214/* Keyboard Beep Counter register. There is a free-running counter inside
215 * the BBC which runs at half the system clock. The bit set in this register
216 * determines when the audio sound is generated. So for example if bit
217 * 10 is set, the audio beep will oscillate at 1/(2**12). The keyboard beep
218 * generator automatically selects a different bit to use if the system clock
219 * is changed via Energy Star.
220 */
221#define BBC_KBD_BCNT_BITS 0x0007fc00
222#define BBC_KBC_BCNT_RESV 0xfff803ff
223
224#endif /* _SPARC64_BBC_H */
225
diff --git a/include/asm-sparc64/chafsr.h b/include/asm-sparc64/chafsr.h
index 85c69b38220b..aaab97562a39 100644
--- a/include/asm-sparc64/chafsr.h
+++ b/include/asm-sparc64/chafsr.h
@@ -1,241 +1 @@
1#ifndef _SPARC64_CHAFSR_H #include <asm-sparc/chafsr.h>
2#define _SPARC64_CHAFSR_H
3
4/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
5
6/* Comments indicate which processor variants on which the bit definition
7 * is valid. Codes are:
8 * ch --> cheetah
9 * ch+ --> cheetah plus
10 * jp --> jalapeno
11 */
12
13/* All bits of this register except M_SYNDROME and E_SYNDROME are
14 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
15 */
16
17/* Software bit set by linux trap handlers to indicate that the trap was
18 * signalled at %tl >= 1.
19 */
20#define CHAFSR_TL1 (1UL << 63UL) /* n/a */
21
22/* Unmapped error from system bus for prefetch queue or
23 * store queue read operation
24 */
25#define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
26
27/* Bus error from system bus for prefetch queue or store queue
28 * read operation
29 */
30#define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
31
32/* Hardware corrected E-cache Tag ECC error */
33#define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
34/* System interface protocol error, hw timeout caused */
35#define JPAFSR_JETO (1UL << 57UL) /* jp */
36
37/* SW handled correctable E-cache Tag ECC error */
38#define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */
39/* Parity error on system snoop results */
40#define JPAFSR_SCE (1UL << 56UL) /* jp */
41
42/* Uncorrectable E-cache Tag ECC error */
43#define CHPAFSR_TUE (1UL << 55UL) /* ch+ */
44/* System interface protocol error, illegal command detected */
45#define JPAFSR_JEIC (1UL << 55UL) /* jp */
46
47/* Uncorrectable system bus data ECC error due to prefetch
48 * or store fill request
49 */
50#define CHPAFSR_DUE (1UL << 54UL) /* ch+ */
51/* System interface protocol error, illegal ADTYPE detected */
52#define JPAFSR_JEIT (1UL << 54UL) /* jp */
53
54/* Multiple errors of the same type have occurred. This bit is set when
55 * an uncorrectable error or a SW correctable error occurs and the status
56 * bit to report that error is already set. When multiple errors of
57 * different types are indicated by setting multiple status bits.
58 *
59 * This bit is not set if multiple HW corrected errors with the same
60 * status bit occur, only uncorrectable and SW correctable ones have
61 * this behavior.
62 *
63 * This bit is not set when multiple ECC errors happen within a single
64 * 64-byte system bus transaction. Only the first ECC error in a 16-byte
65 * subunit will be logged. All errors in subsequent 16-byte subunits
66 * from the same 64-byte transaction are ignored.
67 */
68#define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */
69
70/* Privileged state error has occurred. This is a capture of PSTATE.PRIV
71 * at the time the error is detected.
72 */
73#define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */
74
75/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
76 * bits and record the most recently detected errors. Bits accumulate
77 * errors that have been detected since the last write to clear the bit.
78 */
79
80/* System interface protocol error. The processor asserts its' ERROR
81 * pin when this event occurs and it also logs a specific cause code
82 * into a JTAG scannable flop.
83 */
84#define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */
85
86/* Internal processor error. The processor asserts its' ERROR
87 * pin when this event occurs and it also logs a specific cause code
88 * into a JTAG scannable flop.
89 */
90#define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */
91
92/* System request parity error on incoming address */
93#define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */
94
95/* HW Corrected system bus MTAG ECC error */
96#define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */
97/* Parity error on L2 cache tag SRAM */
98#define JPAFSR_ETP (1UL << 48UL) /* jp */
99
100/* Uncorrectable system bus MTAG ECC error */
101#define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */
102/* Out of range memory error has occurred */
103#define JPAFSR_OM (1UL << 47UL) /* jp */
104
105/* HW Corrected system bus data ECC error for read of interrupt vector */
106#define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */
107/* Error due to unsupported store */
108#define JPAFSR_UMS (1UL << 46UL) /* jp */
109
110/* Uncorrectable system bus data ECC error for read of interrupt vector */
111#define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */
112
113/* Unmapped error from system bus */
114#define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */
115
116/* Bus error response from system bus */
117#define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */
118
119/* SW Correctable E-cache ECC error for instruction fetch or data access
120 * other than block load.
121 */
122#define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */
123
124/* Uncorrectable E-cache ECC error for instruction fetch or data access
125 * other than block load.
126 */
127#define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */
128
129/* Copyout HW Corrected ECC error */
130#define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */
131
132/* Copyout Uncorrectable ECC error */
133#define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */
134
135/* HW Corrected ECC error from E-cache for writeback */
136#define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */
137
138/* Uncorrectable ECC error from E-cache for writeback */
139#define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */
140
141/* HW Corrected ECC error from E-cache for store merge or block load */
142#define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */
143
144/* Uncorrectable ECC error from E-cache for store merge or block load */
145#define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */
146
147/* Uncorrectable system bus data ECC error for read of memory or I/O */
148#define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */
149
150/* HW Corrected system bus data ECC error for read of memory or I/O */
151#define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */
152
153/* Uncorrectable ECC error from remote cache/memory */
154#define JPAFSR_RUE (1UL << 32UL) /* jp */
155
156/* Correctable ECC error from remote cache/memory */
157#define JPAFSR_RCE (1UL << 31UL) /* jp */
158
159/* JBUS parity error on returned read data */
160#define JPAFSR_BP (1UL << 30UL) /* jp */
161
162/* JBUS parity error on data for writeback or block store */
163#define JPAFSR_WBP (1UL << 29UL) /* jp */
164
165/* Foreign read to DRAM incurring correctable ECC error */
166#define JPAFSR_FRC (1UL << 28UL) /* jp */
167
168/* Foreign read to DRAM incurring uncorrectable ECC error */
169#define JPAFSR_FRU (1UL << 27UL) /* jp */
170
171#define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
172 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
173 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
174 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
175 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
176#define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
177 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
178 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
179 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
180 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
181 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
182 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
183#define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
184 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
185 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
186 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
187 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
188 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
189 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
190 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
191 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
192 JPAFSR_FRC | JPAFSR_FRU)
193
194/* Active JBUS request signal when error occurred */
195#define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */
196#define JPAFSR_JBREQ_SHIFT 24UL
197
198/* L2 cache way information */
199#define JPAFSR_ETW (0x3UL << 22UL) /* jp */
200#define JPAFSR_ETW_SHIFT 22UL
201
202/* System bus MTAG ECC syndrome. This field captures the status of the
203 * first occurrence of the highest-priority error according to the M_SYND
204 * overwrite policy. After the AFSR sticky bit, corresponding to the error
205 * for which the M_SYND is reported, is cleared, the contents of the M_SYND
206 * field will be unchanged by will be unfrozen for further error capture.
207 */
208#define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */
209#define CHAFSR_M_SYNDROME_SHIFT 16UL
210
211/* Agenid Id of the foreign device causing the UE/CE errors */
212#define JPAFSR_AID (0x1fUL << 9UL) /* jp */
213#define JPAFSR_AID_SHIFT 9UL
214
215/* System bus or E-cache data ECC syndrome. This field captures the status
216 * of the first occurrence of the highest-priority error according to the
217 * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the
218 * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
219 * field will be unchanged but will be unfrozen for further error capture.
220 */
221#define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */
222#define CHAFSR_E_SYNDROME_SHIFT 0UL
223
224/* The AFSR must be explicitly cleared by software, it is not cleared automatically
225 * by a read. Writes to bits <51:33> with bits set will clear the corresponding
226 * bits in the AFSR. Bits associated with disrupting traps must be cleared before
227 * interrupts are re-enabled to prevent multiple traps for the same error. I.e.
228 * PSTATE.IE and AFSR bits control delivery of disrupting traps.
229 *
230 * Since there is only one AFAR, when multiple events have been logged by the
231 * bits in the AFSR, at most one of these events will have its status captured
232 * in the AFAR. The highest priority of those event bits will get AFAR logging.
233 * The AFAR will be unlocked and available to capture the address of another event
234 * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
235 * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
236 * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
237 * and ready for another event, even though AFSR.CE is still set. The same rules
238 * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
239 */
240
241#endif /* _SPARC64_CHAFSR_H */
diff --git a/include/asm-sparc64/chmctrl.h b/include/asm-sparc64/chmctrl.h
index 859b4a4b0d30..eb757b483b30 100644
--- a/include/asm-sparc64/chmctrl.h
+++ b/include/asm-sparc64/chmctrl.h
@@ -1,183 +1 @@
1#ifndef _SPARC64_CHMCTRL_H #include <asm-sparc/chmctrl.h>
2#define _SPARC64_CHMCTRL_H
3
4/* Cheetah memory controller programmable registers. */
5#define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
6#define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
7#define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
8#define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
9#define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */
10#define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */
11#define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
12#define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */
13#define CHMCTRL_MACTRL 0x30 /* Memory Address Control */
14
15/* Memory Timing Control I */
16#define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL
17#define TCTRL1_SDRAMCTL_DLY_SHIFT 60
18#define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL
19#define TCTRL1_SDRAMCLK_DLY_SHIFT 57
20#define TCTRL1_R 0x0100000000000000UL
21#define TCTRL1_R_SHIFT 56
22#define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL
23#define TCTRL1_AUTORFR_CYCLE_SHIFT 49
24#define TCTRL1_RD_WAIT 0x0001f00000000000UL
25#define TCTRL1_RD_WAIT_SHIFT 44
26#define TCTRL1_PC_CYCLE 0x00000fc000000000UL
27#define TCTRL1_PC_CYCLE_SHIFT 38
28#define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL
29#define TCTRL1_WR_MORE_RAS_PW_SHIFT 32
30#define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL
31#define TCTRL1_RD_MORE_RAS_PW_SHIFT 26
32#define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL
33#define TCTRL1_ACT_WR_DLY_SHIFT 20
34#define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL
35#define TCTRL1_ACT_RD_DLY_SHIFT 14
36#define TCTRL1_BANK_PRESENT 0x0000000000003000UL
37#define TCTRL1_BANK_PRESENT_SHIFT 12
38#define TCTRL1_RFR_INT 0x0000000000000ff8UL
39#define TCTRL1_RFR_INT_SHIFT 3
40#define TCTRL1_SET_MODE_REG 0x0000000000000004UL
41#define TCTRL1_SET_MODE_REG_SHIFT 2
42#define TCTRL1_RFR_ENABLE 0x0000000000000002UL
43#define TCTRL1_RFR_ENABLE_SHIFT 1
44#define TCTRL1_PRECHG_ALL 0x0000000000000001UL
45#define TCTRL1_PRECHG_ALL_SHIFT 0
46
47/* Memory Timing Control II */
48#define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL
49#define TCTRL2_WR_MSEL_DLY_SHIFT 58
50#define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL
51#define TCTRL2_RD_MSEL_DLY_SHIFT 52
52#define TCTRL2_WRDATA_THLD 0x000c000000000000UL
53#define TCTRL2_WRDATA_THLD_SHIFT 50
54#define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL
55#define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44
56#define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL
57#define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43
58#define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL
59#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
60#define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL
61#define TCTRL2_RDWR_1_DLY_SHIFT 32
62#define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL
63#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
64#define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL
65#define TCTRL2_WRWR_1_DLY_SHIFT 21
66#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
67#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
68#define TCTRL2_R 0x0000000000008000UL
69#define TCTRL2_R_SHIFT 15
70#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
71#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
72
73/* Memory Timing Control III */
74#define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL
75#define TCTRL3_SDRAM_CTL_DLY_SHIFT 60
76#define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL
77#define TCTRL3_SDRAM_CLK_DLY_SHIFT 57
78#define TCTRL3_R 0x0100000000000000UL
79#define TCTRL3_R_SHIFT 56
80#define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL
81#define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49
82#define TCTRL3_RD_WAIT 0x0001f00000000000UL
83#define TCTRL3_RD_WAIT_SHIFT 44
84#define TCTRL3_PC_CYCLE 0x00000fc000000000UL
85#define TCTRL3_PC_CYCLE_SHIFT 38
86#define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL
87#define TCTRL3_WR_MORE_RAW_PW_SHIFT 32
88#define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL
89#define TCTRL3_RD_MORE_RAW_PW_SHIFT 26
90#define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL
91#define TCTRL3_ACT_WR_DLY_SHIFT 20
92#define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL
93#define TCTRL3_ACT_RD_DLY_SHIFT 14
94#define TCTRL3_BANK_PRESENT 0x0000000000003000UL
95#define TCTRL3_BANK_PRESENT_SHIFT 12
96#define TCTRL3_RFR_INT 0x0000000000000ff8UL
97#define TCTRL3_RFR_INT_SHIFT 3
98#define TCTRL3_SET_MODE_REG 0x0000000000000004UL
99#define TCTRL3_SET_MODE_REG_SHIFT 2
100#define TCTRL3_RFR_ENABLE 0x0000000000000002UL
101#define TCTRL3_RFR_ENABLE_SHIFT 1
102#define TCTRL3_PRECHG_ALL 0x0000000000000001UL
103#define TCTRL3_PRECHG_ALL_SHIFT 0
104
105/* Memory Timing Control IV */
106#define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL
107#define TCTRL4_WR_MSEL_DLY_SHIFT 58
108#define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL
109#define TCTRL4_RD_MSEL_DLY_SHIFT 52
110#define TCTRL4_WRDATA_THLD 0x000c000000000000UL
111#define TCTRL4_WRDATA_THLD_SHIFT 50
112#define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL
113#define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44
114#define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL
115#define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
116#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
117#define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
118#define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL
119#define TCTRL4_RD_WR_TI_DLY_SHIFT 32
120#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
121#define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
122#define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL
123#define TCTRL4_WR_WR_TI_DLY_SHIFT 21
124#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
125#define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
126#define TCTRL4_R 0x0000000000008000UL
127#define TCTRL4_R_SHIFT 15
128#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
129#define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
130
131/* All 4 memory address decoding registers have the
132 * same layout.
133 */
134#define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */
135#define MEM_DECODE_VALID_SHIFT 63
136#define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */
137#define MEM_DECODE_UK_SHIFT 41
138#define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */
139#define MEM_DECODE_UM_SHIFT 20
140#define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */
141#define MEM_DECODE_LK_SHIFT 14
142#define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */
143#define MEM_DECODE_LM_SHIFT 8
144
145#define PA_UPPER_BITS 0x000007fffc000000UL
146#define PA_UPPER_BITS_SHIFT 26
147#define PA_LOWER_BITS 0x00000000000003c0UL
148#define PA_LOWER_BITS_SHIFT 6
149
150#define MACTRL_R0 0x8000000000000000UL
151#define MACTRL_R0_SHIFT 63
152#define MACTRL_ADDR_LE_PW 0x7000000000000000UL
153#define MACTRL_ADDR_LE_PW_SHIFT 60
154#define MACTRL_CMD_PW 0x0f00000000000000UL
155#define MACTRL_CMD_PW_SHIFT 56
156#define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL
157#define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
158#define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL
159#define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
160#define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL
161#define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
162#define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL
163#define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
164#define MACTRL_R1 0x0000001000000000UL
165#define MACTRL_R1_SHIFT 36
166#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
167#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
168#define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL
169#define MACTRL_ENC_INTLV_B3_SHIFT 27
170#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
171#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
172#define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL
173#define MACTRL_ENC_INTLV_B2_SHIFT 18
174#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
175#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
176#define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL
177#define MACTRL_ENC_INTLV_B1_SHIFT 9
178#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
179#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5
180#define MACTRL_ENC_INTLV_B0 0x000000000000001fUL
181#define MACTRL_ENC_INTLV_B0_SHIFT 0
182
183#endif /* _SPARC64_CHMCTRL_H */
diff --git a/include/asm-sparc64/cmt.h b/include/asm-sparc64/cmt.h
index 870db5928577..b19b445cb810 100644
--- a/include/asm-sparc64/cmt.h
+++ b/include/asm-sparc64/cmt.h
@@ -1,59 +1 @@
1#ifndef _SPARC64_CMT_H #include <asm-sparc/cmt.h>
2#define _SPARC64_CMT_H
3
4/* cmt.h: Chip Multi-Threading register definitions
5 *
6 * Copyright (C) 2004 David S. Miller (davem@redhat.com)
7 */
8
9/* ASI_CORE_ID - private */
10#define LP_ID 0x0000000000000010UL
11#define LP_ID_MAX 0x00000000003f0000UL
12#define LP_ID_ID 0x000000000000003fUL
13
14/* ASI_INTR_ID - private */
15#define LP_INTR_ID 0x0000000000000000UL
16#define LP_INTR_ID_ID 0x00000000000003ffUL
17
18/* ASI_CESR_ID - private */
19#define CESR_ID 0x0000000000000040UL
20#define CESR_ID_ID 0x00000000000000ffUL
21
22/* ASI_CORE_AVAILABLE - shared */
23#define LP_AVAIL 0x0000000000000000UL
24#define LP_AVAIL_1 0x0000000000000002UL
25#define LP_AVAIL_0 0x0000000000000001UL
26
27/* ASI_CORE_ENABLE_STATUS - shared */
28#define LP_ENAB_STAT 0x0000000000000010UL
29#define LP_ENAB_STAT_1 0x0000000000000002UL
30#define LP_ENAB_STAT_0 0x0000000000000001UL
31
32/* ASI_CORE_ENABLE - shared */
33#define LP_ENAB 0x0000000000000020UL
34#define LP_ENAB_1 0x0000000000000002UL
35#define LP_ENAB_0 0x0000000000000001UL
36
37/* ASI_CORE_RUNNING - shared */
38#define LP_RUNNING_RW 0x0000000000000050UL
39#define LP_RUNNING_W1S 0x0000000000000060UL
40#define LP_RUNNING_W1C 0x0000000000000068UL
41#define LP_RUNNING_1 0x0000000000000002UL
42#define LP_RUNNING_0 0x0000000000000001UL
43
44/* ASI_CORE_RUNNING_STAT - shared */
45#define LP_RUN_STAT 0x0000000000000058UL
46#define LP_RUN_STAT_1 0x0000000000000002UL
47#define LP_RUN_STAT_0 0x0000000000000001UL
48
49/* ASI_XIR_STEERING - shared */
50#define LP_XIR_STEER 0x0000000000000030UL
51#define LP_XIR_STEER_1 0x0000000000000002UL
52#define LP_XIR_STEER_0 0x0000000000000001UL
53
54/* ASI_CMT_ERROR_STEERING - shared */
55#define CMT_ER_STEER 0x0000000000000040UL
56#define CMT_ER_STEER_1 0x0000000000000002UL
57#define CMT_ER_STEER_0 0x0000000000000001UL
58
59#endif /* _SPARC64_CMT_H */
diff --git a/include/asm-sparc64/compat.h b/include/asm-sparc64/compat.h
index f260b58f5ce9..8c155d221952 100644
--- a/include/asm-sparc64/compat.h
+++ b/include/asm-sparc64/compat.h
@@ -1,243 +1 @@
1#ifndef _ASM_SPARC64_COMPAT_H #include <asm-sparc/compat.h>
2#define _ASM_SPARC64_COMPAT_H
3/*
4 * Architecture specific compatibility types
5 */
6#include <linux/types.h>
7
8#define COMPAT_USER_HZ 100
9
10typedef u32 compat_size_t;
11typedef s32 compat_ssize_t;
12typedef s32 compat_time_t;
13typedef s32 compat_clock_t;
14typedef s32 compat_pid_t;
15typedef u16 __compat_uid_t;
16typedef u16 __compat_gid_t;
17typedef u32 __compat_uid32_t;
18typedef u32 __compat_gid32_t;
19typedef u16 compat_mode_t;
20typedef u32 compat_ino_t;
21typedef u16 compat_dev_t;
22typedef s32 compat_off_t;
23typedef s64 compat_loff_t;
24typedef s16 compat_nlink_t;
25typedef u16 compat_ipc_pid_t;
26typedef s32 compat_daddr_t;
27typedef u32 compat_caddr_t;
28typedef __kernel_fsid_t compat_fsid_t;
29typedef s32 compat_key_t;
30typedef s32 compat_timer_t;
31
32typedef s32 compat_int_t;
33typedef s32 compat_long_t;
34typedef s64 compat_s64;
35typedef u32 compat_uint_t;
36typedef u32 compat_ulong_t;
37typedef u64 compat_u64;
38
39struct compat_timespec {
40 compat_time_t tv_sec;
41 s32 tv_nsec;
42};
43
44struct compat_timeval {
45 compat_time_t tv_sec;
46 s32 tv_usec;
47};
48
49struct compat_stat {
50 compat_dev_t st_dev;
51 compat_ino_t st_ino;
52 compat_mode_t st_mode;
53 compat_nlink_t st_nlink;
54 __compat_uid_t st_uid;
55 __compat_gid_t st_gid;
56 compat_dev_t st_rdev;
57 compat_off_t st_size;
58 compat_time_t st_atime;
59 compat_ulong_t st_atime_nsec;
60 compat_time_t st_mtime;
61 compat_ulong_t st_mtime_nsec;
62 compat_time_t st_ctime;
63 compat_ulong_t st_ctime_nsec;
64 compat_off_t st_blksize;
65 compat_off_t st_blocks;
66 u32 __unused4[2];
67};
68
69struct compat_stat64 {
70 unsigned long long st_dev;
71
72 unsigned long long st_ino;
73
74 unsigned int st_mode;
75 unsigned int st_nlink;
76
77 unsigned int st_uid;
78 unsigned int st_gid;
79
80 unsigned long long st_rdev;
81
82 unsigned char __pad3[8];
83
84 long long st_size;
85 unsigned int st_blksize;
86
87 unsigned char __pad4[8];
88 unsigned int st_blocks;
89
90 unsigned int st_atime;
91 unsigned int st_atime_nsec;
92
93 unsigned int st_mtime;
94 unsigned int st_mtime_nsec;
95
96 unsigned int st_ctime;
97 unsigned int st_ctime_nsec;
98
99 unsigned int __unused4;
100 unsigned int __unused5;
101};
102
103struct compat_flock {
104 short l_type;
105 short l_whence;
106 compat_off_t l_start;
107 compat_off_t l_len;
108 compat_pid_t l_pid;
109 short __unused;
110};
111
112#define F_GETLK64 12
113#define F_SETLK64 13
114#define F_SETLKW64 14
115
116struct compat_flock64 {
117 short l_type;
118 short l_whence;
119 compat_loff_t l_start;
120 compat_loff_t l_len;
121 compat_pid_t l_pid;
122 short __unused;
123};
124
125struct compat_statfs {
126 int f_type;
127 int f_bsize;
128 int f_blocks;
129 int f_bfree;
130 int f_bavail;
131 int f_files;
132 int f_ffree;
133 compat_fsid_t f_fsid;
134 int f_namelen; /* SunOS ignores this field. */
135 int f_frsize;
136 int f_spare[5];
137};
138
139#define COMPAT_RLIM_INFINITY 0x7fffffff
140
141typedef u32 compat_old_sigset_t;
142
143#define _COMPAT_NSIG 64
144#define _COMPAT_NSIG_BPW 32
145
146typedef u32 compat_sigset_word;
147
148#define COMPAT_OFF_T_MAX 0x7fffffff
149#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
150
151/*
152 * A pointer passed in from user mode. This should not
153 * be used for syscall parameters, just declare them
154 * as pointers because the syscall entry code will have
155 * appropriately converted them already.
156 */
157typedef u32 compat_uptr_t;
158
159static inline void __user *compat_ptr(compat_uptr_t uptr)
160{
161 return (void __user *)(unsigned long)uptr;
162}
163
164static inline compat_uptr_t ptr_to_compat(void __user *uptr)
165{
166 return (u32)(unsigned long)uptr;
167}
168
169static inline void __user *compat_alloc_user_space(long len)
170{
171 struct pt_regs *regs = current_thread_info()->kregs;
172 unsigned long usp = regs->u_regs[UREG_I6];
173
174 if (!(test_thread_flag(TIF_32BIT)))
175 usp += STACK_BIAS;
176 else
177 usp &= 0xffffffffUL;
178
179 usp -= len;
180 usp &= ~0x7UL;
181
182 return (void __user *) usp;
183}
184
185struct compat_ipc64_perm {
186 compat_key_t key;
187 __compat_uid32_t uid;
188 __compat_gid32_t gid;
189 __compat_uid32_t cuid;
190 __compat_gid32_t cgid;
191 unsigned short __pad1;
192 compat_mode_t mode;
193 unsigned short __pad2;
194 unsigned short seq;
195 unsigned long __unused1; /* yes they really are 64bit pads */
196 unsigned long __unused2;
197};
198
199struct compat_semid64_ds {
200 struct compat_ipc64_perm sem_perm;
201 unsigned int __pad1;
202 compat_time_t sem_otime;
203 unsigned int __pad2;
204 compat_time_t sem_ctime;
205 u32 sem_nsems;
206 u32 __unused1;
207 u32 __unused2;
208};
209
210struct compat_msqid64_ds {
211 struct compat_ipc64_perm msg_perm;
212 unsigned int __pad1;
213 compat_time_t msg_stime;
214 unsigned int __pad2;
215 compat_time_t msg_rtime;
216 unsigned int __pad3;
217 compat_time_t msg_ctime;
218 unsigned int msg_cbytes;
219 unsigned int msg_qnum;
220 unsigned int msg_qbytes;
221 compat_pid_t msg_lspid;
222 compat_pid_t msg_lrpid;
223 unsigned int __unused1;
224 unsigned int __unused2;
225};
226
227struct compat_shmid64_ds {
228 struct compat_ipc64_perm shm_perm;
229 unsigned int __pad1;
230 compat_time_t shm_atime;
231 unsigned int __pad2;
232 compat_time_t shm_dtime;
233 unsigned int __pad3;
234 compat_time_t shm_ctime;
235 compat_size_t shm_segsz;
236 compat_pid_t shm_cpid;
237 compat_pid_t shm_lpid;
238 unsigned int shm_nattch;
239 unsigned int __unused1;
240 unsigned int __unused2;
241};
242
243#endif /* _ASM_SPARC64_COMPAT_H */
diff --git a/include/asm-sparc64/compat_signal.h b/include/asm-sparc64/compat_signal.h
index b759eab9b51c..7187dcc8cac7 100644
--- a/include/asm-sparc64/compat_signal.h
+++ b/include/asm-sparc64/compat_signal.h
@@ -1,29 +1 @@
1#ifndef _COMPAT_SIGNAL_H #include <asm-sparc/compat_signal.h>
2#define _COMPAT_SIGNAL_H
3
4#include <linux/compat.h>
5#include <asm/signal.h>
6
7#ifdef CONFIG_COMPAT
8struct __new_sigaction32 {
9 unsigned sa_handler;
10 unsigned int sa_flags;
11 unsigned sa_restorer; /* not used by Linux/SPARC yet */
12 compat_sigset_t sa_mask;
13};
14
15struct __old_sigaction32 {
16 unsigned sa_handler;
17 compat_old_sigset_t sa_mask;
18 unsigned int sa_flags;
19 unsigned sa_restorer; /* not used by Linux/SPARC yet */
20};
21
22typedef struct sigaltstack32 {
23 u32 ss_sp;
24 int ss_flags;
25 compat_size_t ss_size;
26} stack_t32;
27#endif
28
29#endif /* !(_COMPAT_SIGNAL_H) */
diff --git a/include/asm-sparc64/dcr.h b/include/asm-sparc64/dcr.h
index 620c9ba642e9..d67613b1f5fe 100644
--- a/include/asm-sparc64/dcr.h
+++ b/include/asm-sparc64/dcr.h
@@ -1,14 +1 @@
1#ifndef _SPARC64_DCR_H #include <asm-sparc/dcr.h>
2#define _SPARC64_DCR_H
3
4/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
5#define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
6#define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */
7#define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */
8#define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */
9#define DCR_SI 0x0000000000000008 /* Single Instruction Disable */
10#define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
11#define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */
12#define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */
13
14#endif /* _SPARC64_DCR_H */
diff --git a/include/asm-sparc64/dcu.h b/include/asm-sparc64/dcu.h
index 0f704e106a1b..28853f4968d1 100644
--- a/include/asm-sparc64/dcu.h
+++ b/include/asm-sparc64/dcu.h
@@ -1,27 +1 @@
1#ifndef _SPARC64_DCU_H #include <asm-sparc/dcu.h>
2#define _SPARC64_DCU_H
3
4#include <linux/const.h>
5
6/* UltraSparc-III Data Cache Unit Control Register */
7#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
8#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
9#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
10#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
11#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
12#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
13#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
14#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
15#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
16#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
17#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
18#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
19#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
20#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
21#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
22#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
23#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
24#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
25#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
26
27#endif /* _SPARC64_DCU_H */
diff --git a/include/asm-sparc64/estate.h b/include/asm-sparc64/estate.h
index 520c08560d1b..bedd0ef5f19c 100644
--- a/include/asm-sparc64/estate.h
+++ b/include/asm-sparc64/estate.h
@@ -1,49 +1 @@
1#ifndef _SPARC64_ESTATE_H #include <asm-sparc/estate.h>
2#define _SPARC64_ESTATE_H
3
4/* UltraSPARC-III E-cache Error Enable */
5#define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */
6#define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */
7#define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */
8#define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */
9#define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */
10#define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */
11#define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */
12
13/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
14 * errors 2) uncorrectable E-cache errors. Such events only occur on reads
15 * of the E-cache by the local processor for: 1) data loads 2) instruction
16 * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge
17 * 2) writeback 2) copyout. The AFSR bits associated with these traps are
18 * UCC and UCU.
19 */
20
21/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
22 * for uncorrectable ECC errors and system errors.
23 *
24 * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
25 * or system bus BusERR:
26 * 1) As the result of an instruction fetch, will generate instruction_access_error
27 * 2) As the result of a load etc. will generate data_access_error.
28 * 3) As the result of store merge completion, writeback, or copyout will
29 * generate a disrupting ECC_error trap.
30 * 4) As the result of such errors on instruction vector fetch can generate any
31 * of the 3 trap types.
32 *
33 * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
34 * BERR, and TO.
35 */
36
37/* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus
38 * reads resulting in a hardware corrected data or MTAG ECC error will generate an
39 * ECC_error disrupting trap with this bit enabled.
40 *
41 * This same trap will also be generated when a hardware corrected ECC error results
42 * during store merge, writeback, and copyout operations.
43 */
44
45/* In general, if the trap enable bits above are disabled the AFSR bits will still
46 * log the events even though the trap will not be generated by the processor.
47 */
48
49#endif /* _SPARC64_ESTATE_H */
diff --git a/include/asm-sparc64/fhc.h b/include/asm-sparc64/fhc.h
index 788cbc46a116..73eb04c19c47 100644
--- a/include/asm-sparc64/fhc.h
+++ b/include/asm-sparc64/fhc.h
@@ -1,121 +1 @@
1/* #include <asm-sparc/fhc.h>
2 * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
3 *
4 * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
5 */
6
7#ifndef _SPARC64_FHC_H
8#define _SPARC64_FHC_H
9
10#include <linux/timer.h>
11
12#include <asm/oplib.h>
13#include <asm/prom.h>
14#include <asm/upa.h>
15
16struct linux_fhc;
17
18/* Clock board register offsets. */
19#define CLOCK_CTRL 0x00UL /* Main control */
20#define CLOCK_STAT1 0x10UL /* Status one */
21#define CLOCK_STAT2 0x20UL /* Status two */
22#define CLOCK_PWRSTAT 0x30UL /* Power status */
23#define CLOCK_PWRPRES 0x40UL /* Power presence */
24#define CLOCK_TEMP 0x50UL /* Temperature */
25#define CLOCK_IRQDIAG 0x60UL /* IRQ diagnostics */
26#define CLOCK_PWRSTAT2 0x70UL /* Power status two */
27
28#define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */
29#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
30#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
31
32struct linux_central {
33 struct linux_fhc *child;
34 unsigned long cfreg;
35 unsigned long clkregs;
36 unsigned long clkver;
37 int slots;
38 struct device_node *prom_node;
39
40 struct linux_prom_ranges central_ranges[PROMREG_MAX];
41 int num_central_ranges;
42};
43
44/* Firehose controller register offsets */
45struct fhc_regs {
46 unsigned long pregs; /* FHC internal regs */
47#define FHC_PREGS_ID 0x00UL /* FHC ID */
48#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */
49#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */
50#define FHC_ID_MANUF 0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
51#define FHC_ID_RESV 0x00000001 /* Read as one */
52#define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
53#define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
54#define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
55#define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
56#define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
57#define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
58#define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
59#define FHC_RCS_CFATAL 0x02000000 /* Centerplane Fatal Error signalled */
60#define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
61#define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
62#define FHC_CONTROL_ICS 0x00100000 /* Ignore Centerplane Signals */
63#define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
64#define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */
65#define FHC_CONTROL_SLINE 0x00010000 /* Firmware Synchronization Line */
66#define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
67#define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
68#define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
69#define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
70#define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
71#define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */
72#define FHC_CONTROL_IXIST 0x00000200 /* 0=FHC tells clock board it exists */
73#define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/
74#define FHC_CONTROL_LLED 0x00000040 /* 0=Left LED ON */
75#define FHC_CONTROL_MLED 0x00000020 /* 1=Middle LED ON */
76#define FHC_CONTROL_RLED 0x00000010 /* 1=Right LED */
77#define FHC_CONTROL_BPINS 0x00000003 /* Spare Bidirectional Pins */
78#define FHC_PREGS_BSR 0x30UL /* FHC Board Status Register */
79#define FHC_BSR_DA64 0x00040000 /* Port A: 0=128bit 1=64bit data path */
80#define FHC_BSR_DB64 0x00020000 /* Port B: 0=128bit 1=64bit data path */
81#define FHC_BSR_BID 0x0001e000 /* Board ID */
82#define FHC_BSR_SA 0x00001c00 /* Port A UPA Speed (from the pins) */
83#define FHC_BSR_SB 0x00000380 /* Port B UPA Speed (from the pins) */
84#define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */
85#define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */
86#define FHC_BSR_NIA 0x0000001c /* Jumper, bit 18 in PROM space */
87#define FHC_BSR_SI 0x00000001 /* Spare input pin value */
88#define FHC_PREGS_ECC 0x40UL /* FHC ECC Control Register (16 bits) */
89#define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */
90#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
91#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
92#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
93 unsigned long ireg; /* FHC IGN reg */
94#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */
95 unsigned long ffregs; /* FHC fanfail regs */
96#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */
97#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
98 unsigned long sregs; /* FHC system regs */
99#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */
100#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
101 unsigned long uregs; /* FHC uart regs */
102#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */
103#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
104 unsigned long tregs; /* FHC TOD regs */
105#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */
106#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
107};
108
109struct linux_fhc {
110 struct linux_fhc *next;
111 struct linux_central *parent; /* NULL if not central FHC */
112 struct fhc_regs fhc_regs;
113 int board;
114 int jtag_master;
115 struct device_node *prom_node;
116
117 struct linux_prom_ranges fhc_ranges[PROMREG_MAX];
118 int num_fhc_ranges;
119};
120
121#endif /* !(_SPARC64_FHC_H) */
diff --git a/include/asm-sparc64/fpumacro.h b/include/asm-sparc64/fpumacro.h
index cc463fec806f..30d6d0f68bc3 100644
--- a/include/asm-sparc64/fpumacro.h
+++ b/include/asm-sparc64/fpumacro.h
@@ -1,33 +1 @@
1/* fpumacro.h: FPU related macros. #include <asm-sparc/fpumacro.h>
2 *
3 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC64_FPUMACRO_H
8#define _SPARC64_FPUMACRO_H
9
10#include <asm/asi.h>
11#include <asm/visasm.h>
12
13struct fpustate {
14 u32 regs[64];
15};
16
17#define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs)
18
19static inline unsigned long fprs_read(void)
20{
21 unsigned long retval;
22
23 __asm__ __volatile__("rd %%fprs, %0" : "=r" (retval));
24
25 return retval;
26}
27
28static inline void fprs_write(unsigned long val)
29{
30 __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val));
31}
32
33#endif /* !(_SPARC64_FPUMACRO_H) */
diff --git a/include/asm-sparc64/hugetlb.h b/include/asm-sparc64/hugetlb.h
index 412af58926a0..21d8f0a9c243 100644
--- a/include/asm-sparc64/hugetlb.h
+++ b/include/asm-sparc64/hugetlb.h
@@ -1,84 +1 @@
1#ifndef _ASM_SPARC64_HUGETLB_H #include <asm-sparc/hugetlb.h>
2#define _ASM_SPARC64_HUGETLB_H
3
4#include <asm/page.h>
5
6
7void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
8 pte_t *ptep, pte_t pte);
9
10pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
11 pte_t *ptep);
12
13void hugetlb_prefault_arch_hook(struct mm_struct *mm);
14
15static inline int is_hugepage_only_range(struct mm_struct *mm,
16 unsigned long addr,
17 unsigned long len) {
18 return 0;
19}
20
21/*
22 * If the arch doesn't supply something else, assume that hugepage
23 * size aligned regions are ok without further preparation.
24 */
25static inline int prepare_hugepage_range(unsigned long addr, unsigned long len)
26{
27 if (len & ~HPAGE_MASK)
28 return -EINVAL;
29 if (addr & ~HPAGE_MASK)
30 return -EINVAL;
31 return 0;
32}
33
34static inline void hugetlb_free_pgd_range(struct mmu_gather **tlb,
35 unsigned long addr, unsigned long end,
36 unsigned long floor,
37 unsigned long ceiling)
38{
39 free_pgd_range(tlb, addr, end, floor, ceiling);
40}
41
42static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
43 unsigned long addr, pte_t *ptep)
44{
45}
46
47static inline int huge_pte_none(pte_t pte)
48{
49 return pte_none(pte);
50}
51
52static inline pte_t huge_pte_wrprotect(pte_t pte)
53{
54 return pte_wrprotect(pte);
55}
56
57static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
58 unsigned long addr, pte_t *ptep)
59{
60 ptep_set_wrprotect(mm, addr, ptep);
61}
62
63static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
64 unsigned long addr, pte_t *ptep,
65 pte_t pte, int dirty)
66{
67 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
68}
69
70static inline pte_t huge_ptep_get(pte_t *ptep)
71{
72 return *ptep;
73}
74
75static inline int arch_prepare_hugepage(struct page *page)
76{
77 return 0;
78}
79
80static inline void arch_release_hugepage(struct page *page)
81{
82}
83
84#endif /* _ASM_SPARC64_HUGETLB_H */
diff --git a/include/asm-sparc64/hvtramp.h b/include/asm-sparc64/hvtramp.h
index b2b9b947b3a4..fb46bfe934a7 100644
--- a/include/asm-sparc64/hvtramp.h
+++ b/include/asm-sparc64/hvtramp.h
@@ -1,37 +1 @@
1#ifndef _SPARC64_HVTRAP_H #include <asm-sparc/hvtramp.h>
2#define _SPARC64_HVTRAP_H
3
4#ifndef __ASSEMBLY__
5
6#include <linux/types.h>
7
8struct hvtramp_mapping {
9 __u64 vaddr;
10 __u64 tte;
11};
12
13struct hvtramp_descr {
14 __u32 cpu;
15 __u32 num_mappings;
16 __u64 fault_info_va;
17 __u64 fault_info_pa;
18 __u64 thread_reg;
19 struct hvtramp_mapping maps[1];
20};
21
22extern void hv_cpu_startup(unsigned long hvdescr_pa);
23
24#endif
25
26#define HVTRAMP_DESCR_CPU 0x00
27#define HVTRAMP_DESCR_NUM_MAPPINGS 0x04
28#define HVTRAMP_DESCR_FAULT_INFO_VA 0x08
29#define HVTRAMP_DESCR_FAULT_INFO_PA 0x10
30#define HVTRAMP_DESCR_THREAD_REG 0x18
31#define HVTRAMP_DESCR_MAPS 0x20
32
33#define HVTRAMP_MAPPING_VADDR 0x00
34#define HVTRAMP_MAPPING_TTE 0x08
35#define HVTRAMP_MAPPING_SIZE 0x10
36
37#endif /* _SPARC64_HVTRAP_H */
diff --git a/include/asm-sparc64/hypervisor.h b/include/asm-sparc64/hypervisor.h
index 3ad45dff52f8..fe7e51a9e429 100644
--- a/include/asm-sparc64/hypervisor.h
+++ b/include/asm-sparc64/hypervisor.h
@@ -1,2945 +1 @@
1#ifndef _SPARC64_HYPERVISOR_H #include <asm-sparc/hypervisor.h>
2#define _SPARC64_HYPERVISOR_H
3
4/* Sun4v hypervisor interfaces and defines.
5 *
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
9 *
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
14 *
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
23 *
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
27 * follows:
28 *
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
36 *
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
46 *
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
50 */
51
52/* Trap numbers. */
53#define HV_FAST_TRAP 0x80
54#define HV_MMU_MAP_ADDR_TRAP 0x83
55#define HV_MMU_UNMAP_ADDR_TRAP 0x84
56#define HV_TTRACE_ADDENTRY_TRAP 0x85
57#define HV_CORE_TRAP 0xff
58
59/* Error codes. */
60#define HV_EOK 0 /* Successful return */
61#define HV_ENOCPU 1 /* Invalid CPU id */
62#define HV_ENORADDR 2 /* Invalid real address */
63#define HV_ENOINTR 3 /* Invalid interrupt id */
64#define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65#define HV_EBADTSB 5 /* Invalid TSB description */
66#define HV_EINVAL 6 /* Invalid argument */
67#define HV_EBADTRAP 7 /* Invalid function number */
68#define HV_EBADALIGN 8 /* Invalid address alignment */
69#define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70#define HV_ENOACCESS 10 /* No access to resource */
71#define HV_EIO 11 /* I/O error */
72#define HV_ECPUERROR 12 /* CPU in error state */
73#define HV_ENOTSUPPORTED 13 /* Function not supported */
74#define HV_ENOMAP 14 /* No mapping found */
75#define HV_ETOOMANY 15 /* Too many items specified */
76#define HV_ECHANNEL 16 /* Invalid LDC channel */
77#define HV_EBUSY 17 /* Resource busy */
78
79/* mach_exit()
80 * TRAP: HV_FAST_TRAP
81 * FUNCTION: HV_FAST_MACH_EXIT
82 * ARG0: exit code
83 * ERRORS: This service does not return.
84 *
85 * Stop all CPUs in the virtual domain and place them into the stopped
86 * state. The 64-bit exit code may be passed to a service entity as
87 * the domain's exit status. On systems without a service entity, the
88 * domain will undergo a reset, and the boot firmware will be
89 * reloaded.
90 *
91 * This function will never return to the guest that invokes it.
92 *
93 * Note: By convention an exit code of zero denotes a successful exit by
94 * the guest code. A non-zero exit code denotes a guest specific
95 * error indication.
96 *
97 */
98#define HV_FAST_MACH_EXIT 0x00
99
100#ifndef __ASSEMBLY__
101extern void sun4v_mach_exit(unsigned long exit_code);
102#endif
103
104/* Domain services. */
105
106/* mach_desc()
107 * TRAP: HV_FAST_TRAP
108 * FUNCTION: HV_FAST_MACH_DESC
109 * ARG0: buffer
110 * ARG1: length
111 * RET0: status
112 * RET1: length
113 * ERRORS: HV_EBADALIGN Buffer is badly aligned
114 * HV_ENORADDR Buffer is to an illegal real address.
115 * HV_EINVAL Buffer length is too small for complete
116 * machine description.
117 *
118 * Copy the most current machine description into the buffer indicated
119 * by the real address in ARG0. The buffer provided must be 16 byte
120 * aligned. Upon success or HV_EINVAL, this service returns the
121 * actual size of the machine description in the RET1 return value.
122 *
123 * Note: A method of determining the appropriate buffer size for the
124 * machine description is to first call this service with a buffer
125 * length of 0 bytes.
126 */
127#define HV_FAST_MACH_DESC 0x01
128
129#ifndef __ASSEMBLY__
130extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
131 unsigned long buf_len,
132 unsigned long *real_buf_len);
133#endif
134
135/* mach_sir()
136 * TRAP: HV_FAST_TRAP
137 * FUNCTION: HV_FAST_MACH_SIR
138 * ERRORS: This service does not return.
139 *
140 * Perform a software initiated reset of the virtual machine domain.
141 * All CPUs are captured as soon as possible, all hardware devices are
142 * returned to the entry default state, and the domain is restarted at
143 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
144 * of the CPUs. The single CPU restarted is selected as determined by
145 * platform specific policy. Memory is preserved across this
146 * operation.
147 */
148#define HV_FAST_MACH_SIR 0x02
149
150#ifndef __ASSEMBLY__
151extern void sun4v_mach_sir(void);
152#endif
153
154/* mach_set_watchdog()
155 * TRAP: HV_FAST_TRAP
156 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
157 * ARG0: timeout in milliseconds
158 * RET0: status
159 * RET1: time remaining in milliseconds
160 *
161 * A guest uses this API to set a watchdog timer. Once the gues has set
162 * the timer, it must call the timer service again either to disable or
163 * postpone the expiration. If the timer expires before being reset or
164 * disabled, then the hypervisor take a platform specific action leading
165 * to guest termination within a bounded time period. The platform action
166 * may include recovery actions such as reporting the expiration to a
167 * Service Processor, and/or automatically restarting the gues.
168 *
169 * The 'timeout' parameter is specified in milliseconds, however the
170 * implementated granularity is given by the 'watchdog-resolution'
171 * property in the 'platform' node of the guest's machine description.
172 * The largest allowed timeout value is specified by the
173 * 'watchdog-max-timeout' property of the 'platform' node.
174 *
175 * If the 'timeout' argument is not zero, the watchdog timer is set to
176 * expire after a minimum of 'timeout' milliseconds.
177 *
178 * If the 'timeout' argument is zero, the watchdog timer is disabled.
179 *
180 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
181 * property, the hypervisor leaves the watchdog timer state unchanged,
182 * and returns a status of EINVAL.
183 *
184 * The 'time remaining' return value is valid regardless of whether the
185 * return status is EOK or EINVAL. A non-zero return value indicates the
186 * number of milliseconds that were remaining until the timer was to expire.
187 * If less than one millisecond remains, the return value is '1'. If the
188 * watchdog timer was disabled at the time of the call, the return value is
189 * zero.
190 *
191 * If the hypervisor cannot support the exact timeout value requested, but
192 * can support a larger timeout value, the hypervisor may round the actual
193 * timeout to a value larger than the requested timeout, consequently the
194 * 'time remaining' return value may be larger than the previously requested
195 * timeout value.
196 *
197 * Any guest OS debugger should be aware that the watchdog service may be in
198 * use. Consequently, it is recommended that the watchdog service is
199 * disabled upon debugger entry (e.g. reaching a breakpoint), and then
200 * re-enabled upon returning to normal execution. The API has been designed
201 * with this in mind, and the 'time remaining' result of the disable call may
202 * be used directly as the timeout argument of the re-enable call.
203 */
204#define HV_FAST_MACH_SET_WATCHDOG 0x05
205
206#ifndef __ASSEMBLY__
207extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
208 unsigned long *orig_timeout);
209#endif
210
211/* CPU services.
212 *
213 * CPUs represent devices that can execute software threads. A single
214 * chip that contains multiple cores or strands is represented as
215 * multiple CPUs with unique CPU identifiers. CPUs are exported to
216 * OBP via the machine description (and to the OS via the OBP device
217 * tree). CPUs are always in one of three states: stopped, running,
218 * or error.
219 *
220 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
221 * CPU within a logical domain. Operations that are to be performed
222 * on multiple CPUs specify them via a CPU list. A CPU list is an
223 * array in real memory, of which each 16-bit word is a CPU ID. CPU
224 * lists are passed through the API as two arguments. The first is
225 * the number of entries (16-bit words) in the CPU list, and the
226 * second is the (real address) pointer to the CPU ID list.
227 */
228
229/* cpu_start()
230 * TRAP: HV_FAST_TRAP
231 * FUNCTION: HV_FAST_CPU_START
232 * ARG0: CPU ID
233 * ARG1: PC
234 * ARG2: RTBA
235 * ARG3: target ARG0
236 * RET0: status
237 * ERRORS: ENOCPU Invalid CPU ID
238 * EINVAL Target CPU ID is not in the stopped state
239 * ENORADDR Invalid PC or RTBA real address
240 * EBADALIGN Unaligned PC or unaligned RTBA
241 * EWOULDBLOCK Starting resources are not available
242 *
243 * Start CPU with given CPU ID with PC in %pc and with a real trap
244 * base address value of RTBA. The indicated CPU must be in the
245 * stopped state. The supplied RTBA must be aligned on a 256 byte
246 * boundary. On successful completion, the specified CPU will be in
247 * the running state and will be supplied with "target ARG0" in %o0
248 * and RTBA in %tba.
249 */
250#define HV_FAST_CPU_START 0x10
251
252#ifndef __ASSEMBLY__
253extern unsigned long sun4v_cpu_start(unsigned long cpuid,
254 unsigned long pc,
255 unsigned long rtba,
256 unsigned long arg0);
257#endif
258
259/* cpu_stop()
260 * TRAP: HV_FAST_TRAP
261 * FUNCTION: HV_FAST_CPU_STOP
262 * ARG0: CPU ID
263 * RET0: status
264 * ERRORS: ENOCPU Invalid CPU ID
265 * EINVAL Target CPU ID is the current cpu
266 * EINVAL Target CPU ID is not in the running state
267 * EWOULDBLOCK Stopping resources are not available
268 * ENOTSUPPORTED Not supported on this platform
269 *
270 * The specified CPU is stopped. The indicated CPU must be in the
271 * running state. On completion, it will be in the stopped state. It
272 * is not legal to stop the current CPU.
273 *
274 * Note: As this service cannot be used to stop the current cpu, this service
275 * may not be used to stop the last running CPU in a domain. To stop
276 * and exit a running domain, a guest must use the mach_exit() service.
277 */
278#define HV_FAST_CPU_STOP 0x11
279
280#ifndef __ASSEMBLY__
281extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
282#endif
283
284/* cpu_yield()
285 * TRAP: HV_FAST_TRAP
286 * FUNCTION: HV_FAST_CPU_YIELD
287 * RET0: status
288 * ERRORS: No possible error.
289 *
290 * Suspend execution on the current CPU. Execution will resume when
291 * an interrupt (device, %stick_compare, or cross-call) is targeted to
292 * the CPU. On some CPUs, this API may be used by the hypervisor to
293 * save power by disabling hardware strands.
294 */
295#define HV_FAST_CPU_YIELD 0x12
296
297#ifndef __ASSEMBLY__
298extern unsigned long sun4v_cpu_yield(void);
299#endif
300
301/* cpu_qconf()
302 * TRAP: HV_FAST_TRAP
303 * FUNCTION: HV_FAST_CPU_QCONF
304 * ARG0: queue
305 * ARG1: base real address
306 * ARG2: number of entries
307 * RET0: status
308 * ERRORS: ENORADDR Invalid base real address
309 * EINVAL Invalid queue or number of entries is less
310 * than 2 or too large.
311 * EBADALIGN Base real address is not correctly aligned
312 * for size.
313 *
314 * Configure the given queue to be placed at the given base real
315 * address, with the given number of entries. The number of entries
316 * must be a power of 2. The base real address must be aligned
317 * exactly to match the queue size. Each queue entry is 64 bytes
318 * long, so for example a 32 entry queue must be aligned on a 2048
319 * byte real address boundary.
320 *
321 * The specified queue is unconfigured if the number of entries is given
322 * as zero.
323 *
324 * For the current version of this API service, the argument queue is defined
325 * as follows:
326 *
327 * queue description
328 * ----- -------------------------
329 * 0x3c cpu mondo queue
330 * 0x3d device mondo queue
331 * 0x3e resumable error queue
332 * 0x3f non-resumable error queue
333 *
334 * Note: The maximum number of entries for each queue for a specific cpu may
335 * be determined from the machine description.
336 */
337#define HV_FAST_CPU_QCONF 0x14
338#define HV_CPU_QUEUE_CPU_MONDO 0x3c
339#define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
340#define HV_CPU_QUEUE_RES_ERROR 0x3e
341#define HV_CPU_QUEUE_NONRES_ERROR 0x3f
342
343#ifndef __ASSEMBLY__
344extern unsigned long sun4v_cpu_qconf(unsigned long type,
345 unsigned long queue_paddr,
346 unsigned long num_queue_entries);
347#endif
348
349/* cpu_qinfo()
350 * TRAP: HV_FAST_TRAP
351 * FUNCTION: HV_FAST_CPU_QINFO
352 * ARG0: queue
353 * RET0: status
354 * RET1: base real address
355 * RET1: number of entries
356 * ERRORS: EINVAL Invalid queue
357 *
358 * Return the configuration info for the given queue. The base real
359 * address and number of entries of the defined queue are returned.
360 * The queue argument values are the same as for cpu_qconf() above.
361 *
362 * If the specified queue is a valid queue number, but no queue has
363 * been defined, the number of entries will be set to zero and the
364 * base real address returned is undefined.
365 */
366#define HV_FAST_CPU_QINFO 0x15
367
368/* cpu_mondo_send()
369 * TRAP: HV_FAST_TRAP
370 * FUNCTION: HV_FAST_CPU_MONDO_SEND
371 * ARG0-1: CPU list
372 * ARG2: data real address
373 * RET0: status
374 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
375 * is not 2-byte aligned.
376 * ENORADDR Invalid data mondo address, or invalid cpu list
377 * address.
378 * ENOCPU Invalid cpu in CPU list
379 * EWOULDBLOCK Some or all of the listed CPUs did not receive
380 * the mondo
381 * ECPUERROR One or more of the listed CPUs are in error
382 * state, use HV_FAST_CPU_STATE to see which ones
383 * EINVAL CPU list includes caller's CPU ID
384 *
385 * Send a mondo interrupt to the CPUs in the given CPU list with the
386 * 64-bytes at the given data real address. The data must be 64-byte
387 * aligned. The mondo data will be delivered to the cpu_mondo queues
388 * of the recipient CPUs.
389 *
390 * In all cases, error or not, the CPUs in the CPU list to which the
391 * mondo has been successfully delivered will be indicated by having
392 * their entry in CPU list updated with the value 0xffff.
393 */
394#define HV_FAST_CPU_MONDO_SEND 0x42
395
396#ifndef __ASSEMBLY__
397extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
398#endif
399
400/* cpu_myid()
401 * TRAP: HV_FAST_TRAP
402 * FUNCTION: HV_FAST_CPU_MYID
403 * RET0: status
404 * RET1: CPU ID
405 * ERRORS: No errors defined.
406 *
407 * Return the hypervisor ID handle for the current CPU. Use by a
408 * virtual CPU to discover it's own identity.
409 */
410#define HV_FAST_CPU_MYID 0x16
411
412/* cpu_state()
413 * TRAP: HV_FAST_TRAP
414 * FUNCTION: HV_FAST_CPU_STATE
415 * ARG0: CPU ID
416 * RET0: status
417 * RET1: state
418 * ERRORS: ENOCPU Invalid CPU ID
419 *
420 * Retrieve the current state of the CPU with the given CPU ID.
421 */
422#define HV_FAST_CPU_STATE 0x17
423#define HV_CPU_STATE_STOPPED 0x01
424#define HV_CPU_STATE_RUNNING 0x02
425#define HV_CPU_STATE_ERROR 0x03
426
427#ifndef __ASSEMBLY__
428extern long sun4v_cpu_state(unsigned long cpuid);
429#endif
430
431/* cpu_set_rtba()
432 * TRAP: HV_FAST_TRAP
433 * FUNCTION: HV_FAST_CPU_SET_RTBA
434 * ARG0: RTBA
435 * RET0: status
436 * RET1: previous RTBA
437 * ERRORS: ENORADDR Invalid RTBA real address
438 * EBADALIGN RTBA is incorrectly aligned for a trap table
439 *
440 * Set the real trap base address of the local cpu to the given RTBA.
441 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
442 * success the previous value of the RTBA is returned in RET1.
443 *
444 * Note: This service does not affect %tba
445 */
446#define HV_FAST_CPU_SET_RTBA 0x18
447
448/* cpu_set_rtba()
449 * TRAP: HV_FAST_TRAP
450 * FUNCTION: HV_FAST_CPU_GET_RTBA
451 * RET0: status
452 * RET1: previous RTBA
453 * ERRORS: No possible error.
454 *
455 * Returns the current value of RTBA in RET1.
456 */
457#define HV_FAST_CPU_GET_RTBA 0x19
458
459/* MMU services.
460 *
461 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
462 */
463#ifndef __ASSEMBLY__
464struct hv_tsb_descr {
465 unsigned short pgsz_idx;
466 unsigned short assoc;
467 unsigned int num_ttes; /* in TTEs */
468 unsigned int ctx_idx;
469 unsigned int pgsz_mask;
470 unsigned long tsb_base;
471 unsigned long resv;
472};
473#endif
474#define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
475#define HV_TSB_DESCR_ASSOC_OFFSET 0x02
476#define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
477#define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
478#define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
479#define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
480#define HV_TSB_DESCR_RESV_OFFSET 0x18
481
482/* Page size bitmask. */
483#define HV_PGSZ_MASK_8K (1 << 0)
484#define HV_PGSZ_MASK_64K (1 << 1)
485#define HV_PGSZ_MASK_512K (1 << 2)
486#define HV_PGSZ_MASK_4MB (1 << 3)
487#define HV_PGSZ_MASK_32MB (1 << 4)
488#define HV_PGSZ_MASK_256MB (1 << 5)
489#define HV_PGSZ_MASK_2GB (1 << 6)
490#define HV_PGSZ_MASK_16GB (1 << 7)
491
492/* Page size index. The value given in the TSB descriptor must correspond
493 * to the smallest page size specified in the pgsz_mask page size bitmask.
494 */
495#define HV_PGSZ_IDX_8K 0
496#define HV_PGSZ_IDX_64K 1
497#define HV_PGSZ_IDX_512K 2
498#define HV_PGSZ_IDX_4MB 3
499#define HV_PGSZ_IDX_32MB 4
500#define HV_PGSZ_IDX_256MB 5
501#define HV_PGSZ_IDX_2GB 6
502#define HV_PGSZ_IDX_16GB 7
503
504/* MMU fault status area.
505 *
506 * MMU related faults have their status and fault address information
507 * placed into a memory region made available by privileged code. Each
508 * virtual processor must make a mmu_fault_area_conf() call to tell the
509 * hypervisor where that processor's fault status should be stored.
510 *
511 * The fault status block is a multiple of 64-bytes and must be aligned
512 * on a 64-byte boundary.
513 */
514#ifndef __ASSEMBLY__
515struct hv_fault_status {
516 unsigned long i_fault_type;
517 unsigned long i_fault_addr;
518 unsigned long i_fault_ctx;
519 unsigned long i_reserved[5];
520 unsigned long d_fault_type;
521 unsigned long d_fault_addr;
522 unsigned long d_fault_ctx;
523 unsigned long d_reserved[5];
524};
525#endif
526#define HV_FAULT_I_TYPE_OFFSET 0x00
527#define HV_FAULT_I_ADDR_OFFSET 0x08
528#define HV_FAULT_I_CTX_OFFSET 0x10
529#define HV_FAULT_D_TYPE_OFFSET 0x40
530#define HV_FAULT_D_ADDR_OFFSET 0x48
531#define HV_FAULT_D_CTX_OFFSET 0x50
532
533#define HV_FAULT_TYPE_FAST_MISS 1
534#define HV_FAULT_TYPE_FAST_PROT 2
535#define HV_FAULT_TYPE_MMU_MISS 3
536#define HV_FAULT_TYPE_INV_RA 4
537#define HV_FAULT_TYPE_PRIV_VIOL 5
538#define HV_FAULT_TYPE_PROT_VIOL 6
539#define HV_FAULT_TYPE_NFO 7
540#define HV_FAULT_TYPE_NFO_SEFF 8
541#define HV_FAULT_TYPE_INV_VA 9
542#define HV_FAULT_TYPE_INV_ASI 10
543#define HV_FAULT_TYPE_NC_ATOMIC 11
544#define HV_FAULT_TYPE_PRIV_ACT 12
545#define HV_FAULT_TYPE_RESV1 13
546#define HV_FAULT_TYPE_UNALIGNED 14
547#define HV_FAULT_TYPE_INV_PGSZ 15
548/* Values 16 --> -2 are reserved. */
549#define HV_FAULT_TYPE_MULTIPLE -1
550
551/* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
552 * and mmu_{map,unmap}_perm_addr().
553 */
554#define HV_MMU_DMMU 0x01
555#define HV_MMU_IMMU 0x02
556#define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
557
558/* mmu_map_addr()
559 * TRAP: HV_MMU_MAP_ADDR_TRAP
560 * ARG0: virtual address
561 * ARG1: mmu context
562 * ARG2: TTE
563 * ARG3: flags (HV_MMU_{IMMU,DMMU})
564 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
565 * EBADPGSZ Invalid page size value
566 * ENORADDR Invalid real address in TTE
567 *
568 * Create a non-permanent mapping using the given TTE, virtual
569 * address, and mmu context. The flags argument determines which
570 * (data, or instruction, or both) TLB the mapping gets loaded into.
571 *
572 * The behavior is undefined if the valid bit is clear in the TTE.
573 *
574 * Note: This API call is for privileged code to specify temporary translation
575 * mappings without the need to create and manage a TSB.
576 */
577
578/* mmu_unmap_addr()
579 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
580 * ARG0: virtual address
581 * ARG1: mmu context
582 * ARG2: flags (HV_MMU_{IMMU,DMMU})
583 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
584 *
585 * Demaps the given virtual address in the given mmu context on this
586 * CPU. This function is intended to be used to demap pages mapped
587 * with mmu_map_addr. This service is equivalent to invoking
588 * mmu_demap_page() with only the current CPU in the CPU list. The
589 * flags argument determines which (data, or instruction, or both) TLB
590 * the mapping gets unmapped from.
591 *
592 * Attempting to perform an unmap operation for a previously defined
593 * permanent mapping will have undefined results.
594 */
595
596/* mmu_tsb_ctx0()
597 * TRAP: HV_FAST_TRAP
598 * FUNCTION: HV_FAST_MMU_TSB_CTX0
599 * ARG0: number of TSB descriptions
600 * ARG1: TSB descriptions pointer
601 * RET0: status
602 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
603 * TSB base within a descriptor
604 * EBADALIGN TSB descriptions pointer is not aligned
605 * to an 8-byte boundary, or TSB base
606 * within a descriptor is not aligned for
607 * the given TSB size
608 * EBADPGSZ Invalid page size in a TSB descriptor
609 * EBADTSB Invalid associativity or size in a TSB
610 * descriptor
611 * EINVAL Invalid number of TSB descriptions, or
612 * invalid context index in a TSB
613 * descriptor, or index page size not
614 * equal to smallest page size in page
615 * size bitmask field.
616 *
617 * Configures the TSBs for the current CPU for virtual addresses with
618 * context zero. The TSB descriptions pointer is a pointer to an
619 * array of the given number of TSB descriptions.
620 *
621 * Note: The maximum number of TSBs available to a virtual CPU is given by the
622 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
623 * machine description.
624 */
625#define HV_FAST_MMU_TSB_CTX0 0x20
626
627#ifndef __ASSEMBLY__
628extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
629 unsigned long tsb_desc_ra);
630#endif
631
632/* mmu_tsb_ctxnon0()
633 * TRAP: HV_FAST_TRAP
634 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
635 * ARG0: number of TSB descriptions
636 * ARG1: TSB descriptions pointer
637 * RET0: status
638 * ERRORS: Same as for mmu_tsb_ctx0() above.
639 *
640 * Configures the TSBs for the current CPU for virtual addresses with
641 * non-zero contexts. The TSB descriptions pointer is a pointer to an
642 * array of the given number of TSB descriptions.
643 *
644 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
645 */
646#define HV_FAST_MMU_TSB_CTXNON0 0x21
647
648/* mmu_demap_page()
649 * TRAP: HV_FAST_TRAP
650 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
651 * ARG0: reserved, must be zero
652 * ARG1: reserved, must be zero
653 * ARG2: virtual address
654 * ARG3: mmu context
655 * ARG4: flags (HV_MMU_{IMMU,DMMU})
656 * RET0: status
657 * ERRORS: EINVAL Invalid virutal address, context, or
658 * flags value
659 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
660 *
661 * Demaps any page mapping of the given virtual address in the given
662 * mmu context for the current virtual CPU. Any virtually tagged
663 * caches are guaranteed to be kept consistent. The flags argument
664 * determines which TLB (instruction, or data, or both) participate in
665 * the operation.
666 *
667 * ARG0 and ARG1 are both reserved and must be set to zero.
668 */
669#define HV_FAST_MMU_DEMAP_PAGE 0x22
670
671/* mmu_demap_ctx()
672 * TRAP: HV_FAST_TRAP
673 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
674 * ARG0: reserved, must be zero
675 * ARG1: reserved, must be zero
676 * ARG2: mmu context
677 * ARG3: flags (HV_MMU_{IMMU,DMMU})
678 * RET0: status
679 * ERRORS: EINVAL Invalid context or flags value
680 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
681 *
682 * Demaps all non-permanent virtual page mappings previously specified
683 * for the given context for the current virtual CPU. Any virtual
684 * tagged caches are guaranteed to be kept consistent. The flags
685 * argument determines which TLB (instruction, or data, or both)
686 * participate in the operation.
687 *
688 * ARG0 and ARG1 are both reserved and must be set to zero.
689 */
690#define HV_FAST_MMU_DEMAP_CTX 0x23
691
692/* mmu_demap_all()
693 * TRAP: HV_FAST_TRAP
694 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
695 * ARG0: reserved, must be zero
696 * ARG1: reserved, must be zero
697 * ARG2: flags (HV_MMU_{IMMU,DMMU})
698 * RET0: status
699 * ERRORS: EINVAL Invalid flags value
700 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
701 *
702 * Demaps all non-permanent virtual page mappings previously specified
703 * for the current virtual CPU. Any virtual tagged caches are
704 * guaranteed to be kept consistent. The flags argument determines
705 * which TLB (instruction, or data, or both) participate in the
706 * operation.
707 *
708 * ARG0 and ARG1 are both reserved and must be set to zero.
709 */
710#define HV_FAST_MMU_DEMAP_ALL 0x24
711
712#ifndef __ASSEMBLY__
713extern void sun4v_mmu_demap_all(void);
714#endif
715
716/* mmu_map_perm_addr()
717 * TRAP: HV_FAST_TRAP
718 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
719 * ARG0: virtual address
720 * ARG1: reserved, must be zero
721 * ARG2: TTE
722 * ARG3: flags (HV_MMU_{IMMU,DMMU})
723 * RET0: status
724 * ERRORS: EINVAL Invalid virutal address or flags value
725 * EBADPGSZ Invalid page size value
726 * ENORADDR Invalid real address in TTE
727 * ETOOMANY Too many mappings (max of 8 reached)
728 *
729 * Create a permanent mapping using the given TTE and virtual address
730 * for context 0 on the calling virtual CPU. A maximum of 8 such
731 * permanent mappings may be specified by privileged code. Mappings
732 * may be removed with mmu_unmap_perm_addr().
733 *
734 * The behavior is undefined if a TTE with the valid bit clear is given.
735 *
736 * Note: This call is used to specify address space mappings for which
737 * privileged code does not expect to receive misses. For example,
738 * this mechanism can be used to map kernel nucleus code and data.
739 */
740#define HV_FAST_MMU_MAP_PERM_ADDR 0x25
741
742#ifndef __ASSEMBLY__
743extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
744 unsigned long set_to_zero,
745 unsigned long tte,
746 unsigned long flags);
747#endif
748
749/* mmu_fault_area_conf()
750 * TRAP: HV_FAST_TRAP
751 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
752 * ARG0: real address
753 * RET0: status
754 * RET1: previous mmu fault area real address
755 * ERRORS: ENORADDR Invalid real address
756 * EBADALIGN Invalid alignment for fault area
757 *
758 * Configure the MMU fault status area for the calling CPU. A 64-byte
759 * aligned real address specifies where MMU fault status information
760 * is placed. The return value is the previously specified area, or 0
761 * for the first invocation. Specifying a fault area at real address
762 * 0 is not allowed.
763 */
764#define HV_FAST_MMU_FAULT_AREA_CONF 0x26
765
766/* mmu_enable()
767 * TRAP: HV_FAST_TRAP
768 * FUNCTION: HV_FAST_MMU_ENABLE
769 * ARG0: enable flag
770 * ARG1: return target address
771 * RET0: status
772 * ERRORS: ENORADDR Invalid real address when disabling
773 * translation.
774 * EBADALIGN The return target address is not
775 * aligned to an instruction.
776 * EINVAL The enable flag request the current
777 * operating mode (e.g. disable if already
778 * disabled)
779 *
780 * Enable or disable virtual address translation for the calling CPU
781 * within the virtual machine domain. If the enable flag is zero,
782 * translation is disabled, any non-zero value will enable
783 * translation.
784 *
785 * When this function returns, the newly selected translation mode
786 * will be active. If the mmu is being enabled, then the return
787 * target address is a virtual address else it is a real address.
788 *
789 * Upon successful completion, control will be returned to the given
790 * return target address (ie. the cpu will jump to that address). On
791 * failure, the previous mmu mode remains and the trap simply returns
792 * as normal with the appropriate error code in RET0.
793 */
794#define HV_FAST_MMU_ENABLE 0x27
795
796/* mmu_unmap_perm_addr()
797 * TRAP: HV_FAST_TRAP
798 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
799 * ARG0: virtual address
800 * ARG1: reserved, must be zero
801 * ARG2: flags (HV_MMU_{IMMU,DMMU})
802 * RET0: status
803 * ERRORS: EINVAL Invalid virutal address or flags value
804 * ENOMAP Specified mapping was not found
805 *
806 * Demaps any permanent page mapping (established via
807 * mmu_map_perm_addr()) at the given virtual address for context 0 on
808 * the current virtual CPU. Any virtual tagged caches are guaranteed
809 * to be kept consistent.
810 */
811#define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
812
813/* mmu_tsb_ctx0_info()
814 * TRAP: HV_FAST_TRAP
815 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
816 * ARG0: max TSBs
817 * ARG1: buffer pointer
818 * RET0: status
819 * RET1: number of TSBs
820 * ERRORS: EINVAL Supplied buffer is too small
821 * EBADALIGN The buffer pointer is badly aligned
822 * ENORADDR Invalid real address for buffer pointer
823 *
824 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
825 * into the provided buffer. The size of the buffer is given in ARG1
826 * in terms of the number of TSB description entries.
827 *
828 * Upon return, RET1 always contains the number of TSB descriptions
829 * previously configured. If zero TSBs were configured, EOK is
830 * returned with RET1 containing 0.
831 */
832#define HV_FAST_MMU_TSB_CTX0_INFO 0x29
833
834/* mmu_tsb_ctxnon0_info()
835 * TRAP: HV_FAST_TRAP
836 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
837 * ARG0: max TSBs
838 * ARG1: buffer pointer
839 * RET0: status
840 * RET1: number of TSBs
841 * ERRORS: EINVAL Supplied buffer is too small
842 * EBADALIGN The buffer pointer is badly aligned
843 * ENORADDR Invalid real address for buffer pointer
844 *
845 * Return the TSB configuration as previous defined by
846 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
847 * is given in ARG1 in terms of the number of TSB description entries.
848 *
849 * Upon return, RET1 always contains the number of TSB descriptions
850 * previously configured. If zero TSBs were configured, EOK is
851 * returned with RET1 containing 0.
852 */
853#define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
854
855/* mmu_fault_area_info()
856 * TRAP: HV_FAST_TRAP
857 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
858 * RET0: status
859 * RET1: fault area real address
860 * ERRORS: No errors defined.
861 *
862 * Return the currently defined MMU fault status area for the current
863 * CPU. The real address of the fault status area is returned in
864 * RET1, or 0 is returned in RET1 if no fault status area is defined.
865 *
866 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
867 * from this service if there is a need to save and restore the fault
868 * area for a cpu.
869 */
870#define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
871
872/* Cache and Memory services. */
873
874/* mem_scrub()
875 * TRAP: HV_FAST_TRAP
876 * FUNCTION: HV_FAST_MEM_SCRUB
877 * ARG0: real address
878 * ARG1: length
879 * RET0: status
880 * RET1: length scrubbed
881 * ERRORS: ENORADDR Invalid real address
882 * EBADALIGN Start address or length are not correctly
883 * aligned
884 * EINVAL Length is zero
885 *
886 * Zero the memory contents in the range real address to real address
887 * plus length minus 1. Also, valid ECC will be generated for that
888 * memory address range. Scrubbing is started at the given real
889 * address, but may not scrub the entire given length. The actual
890 * length scrubbed will be returned in RET1.
891 *
892 * The real address and length must be aligned on an 8K boundary, or
893 * contain the start address and length from a sun4v error report.
894 *
895 * Note: There are two uses for this function. The first use is to block clear
896 * and initialize memory and the second is to scrub an u ncorrectable
897 * error reported via a resumable or non-resumable trap. The second
898 * use requires the arguments to be equal to the real address and length
899 * provided in a sun4v memory error report.
900 */
901#define HV_FAST_MEM_SCRUB 0x31
902
903/* mem_sync()
904 * TRAP: HV_FAST_TRAP
905 * FUNCTION: HV_FAST_MEM_SYNC
906 * ARG0: real address
907 * ARG1: length
908 * RET0: status
909 * RET1: length synced
910 * ERRORS: ENORADDR Invalid real address
911 * EBADALIGN Start address or length are not correctly
912 * aligned
913 * EINVAL Length is zero
914 *
915 * Force the next access within the real address to real address plus
916 * length minus 1 to be fetches from main system memory. Less than
917 * the given length may be synced, the actual amount synced is
918 * returned in RET1. The real address and length must be aligned on
919 * an 8K boundary.
920 */
921#define HV_FAST_MEM_SYNC 0x32
922
923/* Time of day services.
924 *
925 * The hypervisor maintains the time of day on a per-domain basis.
926 * Changing the time of day in one domain does not affect the time of
927 * day on any other domain.
928 *
929 * Time is described by a single unsigned 64-bit word which is the
930 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
931 * 1970).
932 */
933
934/* tod_get()
935 * TRAP: HV_FAST_TRAP
936 * FUNCTION: HV_FAST_TOD_GET
937 * RET0: status
938 * RET1: TOD
939 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
940 * ENOTSUPPORTED If TOD not supported on this platform
941 *
942 * Return the current time of day. May block if TOD access is
943 * temporarily not possible.
944 */
945#define HV_FAST_TOD_GET 0x50
946
947#ifndef __ASSEMBLY__
948extern unsigned long sun4v_tod_get(unsigned long *time);
949#endif
950
951/* tod_set()
952 * TRAP: HV_FAST_TRAP
953 * FUNCTION: HV_FAST_TOD_SET
954 * ARG0: TOD
955 * RET0: status
956 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
957 * ENOTSUPPORTED If TOD not supported on this platform
958 *
959 * The current time of day is set to the value specified in ARG0. May
960 * block if TOD access is temporarily not possible.
961 */
962#define HV_FAST_TOD_SET 0x51
963
964#ifndef __ASSEMBLY__
965extern unsigned long sun4v_tod_set(unsigned long time);
966#endif
967
968/* Console services */
969
970/* con_getchar()
971 * TRAP: HV_FAST_TRAP
972 * FUNCTION: HV_FAST_CONS_GETCHAR
973 * RET0: status
974 * RET1: character
975 * ERRORS: EWOULDBLOCK No character available.
976 *
977 * Returns a character from the console device. If no character is
978 * available then an EWOULDBLOCK error is returned. If a character is
979 * available, then the returned status is EOK and the character value
980 * is in RET1.
981 *
982 * A virtual BREAK is represented by the 64-bit value -1.
983 *
984 * A virtual HUP signal is represented by the 64-bit value -2.
985 */
986#define HV_FAST_CONS_GETCHAR 0x60
987
988/* con_putchar()
989 * TRAP: HV_FAST_TRAP
990 * FUNCTION: HV_FAST_CONS_PUTCHAR
991 * ARG0: character
992 * RET0: status
993 * ERRORS: EINVAL Illegal character
994 * EWOULDBLOCK Output buffer currently full, would block
995 *
996 * Send a character to the console device. Only character values
997 * between 0 and 255 may be used. Values outside this range are
998 * invalid except for the 64-bit value -1 which is used to send a
999 * virtual BREAK.
1000 */
1001#define HV_FAST_CONS_PUTCHAR 0x61
1002
1003/* con_read()
1004 * TRAP: HV_FAST_TRAP
1005 * FUNCTION: HV_FAST_CONS_READ
1006 * ARG0: buffer real address
1007 * ARG1: buffer size in bytes
1008 * RET0: status
1009 * RET1: bytes read or BREAK or HUP
1010 * ERRORS: EWOULDBLOCK No character available.
1011 *
1012 * Reads characters into a buffer from the console device. If no
1013 * character is available then an EWOULDBLOCK error is returned.
1014 * If a character is available, then the returned status is EOK
1015 * and the number of bytes read into the given buffer is provided
1016 * in RET1.
1017 *
1018 * A virtual BREAK is represented by the 64-bit RET1 value -1.
1019 *
1020 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1021 *
1022 * If BREAK or HUP are indicated, no bytes were read into buffer.
1023 */
1024#define HV_FAST_CONS_READ 0x62
1025
1026/* con_write()
1027 * TRAP: HV_FAST_TRAP
1028 * FUNCTION: HV_FAST_CONS_WRITE
1029 * ARG0: buffer real address
1030 * ARG1: buffer size in bytes
1031 * RET0: status
1032 * RET1: bytes written
1033 * ERRORS: EWOULDBLOCK Output buffer currently full, would block
1034 *
1035 * Send a characters in buffer to the console device. Breaks must be
1036 * sent using con_putchar().
1037 */
1038#define HV_FAST_CONS_WRITE 0x63
1039
1040#ifndef __ASSEMBLY__
1041extern long sun4v_con_getchar(long *status);
1042extern long sun4v_con_putchar(long c);
1043extern long sun4v_con_read(unsigned long buffer,
1044 unsigned long size,
1045 unsigned long *bytes_read);
1046extern unsigned long sun4v_con_write(unsigned long buffer,
1047 unsigned long size,
1048 unsigned long *bytes_written);
1049#endif
1050
1051/* mach_set_soft_state()
1052 * TRAP: HV_FAST_TRAP
1053 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
1054 * ARG0: software state
1055 * ARG1: software state description pointer
1056 * RET0: status
1057 * ERRORS: EINVAL software state not valid or software state
1058 * description is not NULL terminated
1059 * ENORADDR software state description pointer is not a
1060 * valid real address
1061 * EBADALIGNED software state description is not correctly
1062 * aligned
1063 *
1064 * This allows the guest to report it's soft state to the hypervisor. There
1065 * are two primary components to this state. The first part states whether
1066 * the guest software is running or not. The second containts optional
1067 * details specific to the software.
1068 *
1069 * The software state argument is defined below in HV_SOFT_STATE_*, and
1070 * indicates whether the guest is operating normally or in a transitional
1071 * state.
1072 *
1073 * The software state description argument is a real address of a data buffer
1074 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
1075 * terminated 7-bit ASCII string of up to 31 characters not including the
1076 * NULL termination.
1077 */
1078#define HV_FAST_MACH_SET_SOFT_STATE 0x70
1079#define HV_SOFT_STATE_NORMAL 0x01
1080#define HV_SOFT_STATE_TRANSITION 0x02
1081
1082#ifndef __ASSEMBLY__
1083extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1084 unsigned long msg_string_ra);
1085#endif
1086
1087/* mach_get_soft_state()
1088 * TRAP: HV_FAST_TRAP
1089 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
1090 * ARG0: software state description pointer
1091 * RET0: status
1092 * RET1: software state
1093 * ERRORS: ENORADDR software state description pointer is not a
1094 * valid real address
1095 * EBADALIGNED software state description is not correctly
1096 * aligned
1097 *
1098 * Retrieve the current value of the guest's software state. The rules
1099 * for the software state pointer are the same as for mach_set_soft_state()
1100 * above.
1101 */
1102#define HV_FAST_MACH_GET_SOFT_STATE 0x71
1103
1104/* svc_send()
1105 * TRAP: HV_FAST_TRAP
1106 * FUNCTION: HV_FAST_SVC_SEND
1107 * ARG0: service ID
1108 * ARG1: buffer real address
1109 * ARG2: buffer size
1110 * RET0: STATUS
1111 * RET1: sent_bytes
1112 *
1113 * Be careful, all output registers are clobbered by this operation,
1114 * so for example it is not possible to save away a value in %o4
1115 * across the trap.
1116 */
1117#define HV_FAST_SVC_SEND 0x80
1118
1119/* svc_recv()
1120 * TRAP: HV_FAST_TRAP
1121 * FUNCTION: HV_FAST_SVC_RECV
1122 * ARG0: service ID
1123 * ARG1: buffer real address
1124 * ARG2: buffer size
1125 * RET0: STATUS
1126 * RET1: recv_bytes
1127 *
1128 * Be careful, all output registers are clobbered by this operation,
1129 * so for example it is not possible to save away a value in %o4
1130 * across the trap.
1131 */
1132#define HV_FAST_SVC_RECV 0x81
1133
1134/* svc_getstatus()
1135 * TRAP: HV_FAST_TRAP
1136 * FUNCTION: HV_FAST_SVC_GETSTATUS
1137 * ARG0: service ID
1138 * RET0: STATUS
1139 * RET1: status bits
1140 */
1141#define HV_FAST_SVC_GETSTATUS 0x82
1142
1143/* svc_setstatus()
1144 * TRAP: HV_FAST_TRAP
1145 * FUNCTION: HV_FAST_SVC_SETSTATUS
1146 * ARG0: service ID
1147 * ARG1: bits to set
1148 * RET0: STATUS
1149 */
1150#define HV_FAST_SVC_SETSTATUS 0x83
1151
1152/* svc_clrstatus()
1153 * TRAP: HV_FAST_TRAP
1154 * FUNCTION: HV_FAST_SVC_CLRSTATUS
1155 * ARG0: service ID
1156 * ARG1: bits to clear
1157 * RET0: STATUS
1158 */
1159#define HV_FAST_SVC_CLRSTATUS 0x84
1160
1161#ifndef __ASSEMBLY__
1162extern unsigned long sun4v_svc_send(unsigned long svc_id,
1163 unsigned long buffer,
1164 unsigned long buffer_size,
1165 unsigned long *sent_bytes);
1166extern unsigned long sun4v_svc_recv(unsigned long svc_id,
1167 unsigned long buffer,
1168 unsigned long buffer_size,
1169 unsigned long *recv_bytes);
1170extern unsigned long sun4v_svc_getstatus(unsigned long svc_id,
1171 unsigned long *status_bits);
1172extern unsigned long sun4v_svc_setstatus(unsigned long svc_id,
1173 unsigned long status_bits);
1174extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
1175 unsigned long status_bits);
1176#endif
1177
1178/* Trap trace services.
1179 *
1180 * The hypervisor provides a trap tracing capability for privileged
1181 * code running on each virtual CPU. Privileged code provides a
1182 * round-robin trap trace queue within which the hypervisor writes
1183 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1184 * privileged code. This is provided as a debugging capability for
1185 * privileged code.
1186 *
1187 * The trap trace control structure is 64-bytes long and placed at the
1188 * start (offset 0) of the trap trace buffer, and is described as
1189 * follows:
1190 */
1191#ifndef __ASSEMBLY__
1192struct hv_trap_trace_control {
1193 unsigned long head_offset;
1194 unsigned long tail_offset;
1195 unsigned long __reserved[0x30 / sizeof(unsigned long)];
1196};
1197#endif
1198#define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
1199#define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
1200
1201/* The head offset is the offset of the most recently completed entry
1202 * in the trap-trace buffer. The tail offset is the offset of the
1203 * next entry to be written. The control structure is owned and
1204 * modified by the hypervisor. A guest may not modify the control
1205 * structure contents. Attempts to do so will result in undefined
1206 * behavior for the guest.
1207 *
1208 * Each trap trace buffer entry is layed out as follows:
1209 */
1210#ifndef __ASSEMBLY__
1211struct hv_trap_trace_entry {
1212 unsigned char type; /* Hypervisor or guest entry? */
1213 unsigned char hpstate; /* Hyper-privileged state */
1214 unsigned char tl; /* Trap level */
1215 unsigned char gl; /* Global register level */
1216 unsigned short tt; /* Trap type */
1217 unsigned short tag; /* Extended trap identifier */
1218 unsigned long tstate; /* Trap state */
1219 unsigned long tick; /* Tick */
1220 unsigned long tpc; /* Trap PC */
1221 unsigned long f1; /* Entry specific */
1222 unsigned long f2; /* Entry specific */
1223 unsigned long f3; /* Entry specific */
1224 unsigned long f4; /* Entry specific */
1225};
1226#endif
1227#define HV_TRAP_TRACE_ENTRY_TYPE 0x00
1228#define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
1229#define HV_TRAP_TRACE_ENTRY_TL 0x02
1230#define HV_TRAP_TRACE_ENTRY_GL 0x03
1231#define HV_TRAP_TRACE_ENTRY_TT 0x04
1232#define HV_TRAP_TRACE_ENTRY_TAG 0x06
1233#define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
1234#define HV_TRAP_TRACE_ENTRY_TICK 0x10
1235#define HV_TRAP_TRACE_ENTRY_TPC 0x18
1236#define HV_TRAP_TRACE_ENTRY_F1 0x20
1237#define HV_TRAP_TRACE_ENTRY_F2 0x28
1238#define HV_TRAP_TRACE_ENTRY_F3 0x30
1239#define HV_TRAP_TRACE_ENTRY_F4 0x38
1240
1241/* The type field is encoded as follows. */
1242#define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
1243#define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
1244#define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1245
1246/* ttrace_buf_conf()
1247 * TRAP: HV_FAST_TRAP
1248 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1249 * ARG0: real address
1250 * ARG1: number of entries
1251 * RET0: status
1252 * RET1: number of entries
1253 * ERRORS: ENORADDR Invalid real address
1254 * EINVAL Size is too small
1255 * EBADALIGN Real address not aligned on 64-byte boundary
1256 *
1257 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1258 * trace buffer to the hypervisor. The real address supplies the real
1259 * base address of the trap trace queue and must be 64-byte aligned.
1260 * Specifying a value of 0 for the number of entries disables trap
1261 * tracing for the calling virtual CPU. The buffer allocated must be
1262 * sized for a power of two number of 64-byte trap trace entries plus
1263 * an initial 64-byte control structure.
1264 *
1265 * This may be invoked any number of times so that a virtual CPU may
1266 * relocate a trap trace buffer or create "snapshots" of information.
1267 *
1268 * If the real address is illegal or badly aligned, then trap tracing
1269 * is disabled and an error is returned.
1270 *
1271 * Upon failure with EINVAL, this service call returns in RET1 the
1272 * minimum number of buffer entries required. Upon other failures
1273 * RET1 is undefined.
1274 */
1275#define HV_FAST_TTRACE_BUF_CONF 0x90
1276
1277/* ttrace_buf_info()
1278 * TRAP: HV_FAST_TRAP
1279 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1280 * RET0: status
1281 * RET1: real address
1282 * RET2: size
1283 * ERRORS: None defined.
1284 *
1285 * Returns the size and location of the previously declared trap-trace
1286 * buffer. In the event that no buffer was previously defined, or the
1287 * buffer is disabled, this call will return a size of zero bytes.
1288 */
1289#define HV_FAST_TTRACE_BUF_INFO 0x91
1290
1291/* ttrace_enable()
1292 * TRAP: HV_FAST_TRAP
1293 * FUNCTION: HV_FAST_TTRACE_ENABLE
1294 * ARG0: enable
1295 * RET0: status
1296 * RET1: previous enable state
1297 * ERRORS: EINVAL No trap trace buffer currently defined
1298 *
1299 * Enable or disable trap tracing, and return the previous enabled
1300 * state in RET1. Future systems may define various flags for the
1301 * enable argument (ARG0), for the moment a guest should pass
1302 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1303 * tracing - which will ensure future compatability.
1304 */
1305#define HV_FAST_TTRACE_ENABLE 0x92
1306
1307/* ttrace_freeze()
1308 * TRAP: HV_FAST_TRAP
1309 * FUNCTION: HV_FAST_TTRACE_FREEZE
1310 * ARG0: freeze
1311 * RET0: status
1312 * RET1: previous freeze state
1313 * ERRORS: EINVAL No trap trace buffer currently defined
1314 *
1315 * Freeze or unfreeze trap tracing, returning the previous freeze
1316 * state in RET1. A guest should pass a non-zero value to freeze and
1317 * a zero value to unfreeze all tracing. The returned previous state
1318 * is 0 for not frozen and 1 for frozen.
1319 */
1320#define HV_FAST_TTRACE_FREEZE 0x93
1321
1322/* ttrace_addentry()
1323 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1324 * ARG0: tag (16-bits)
1325 * ARG1: data word 0
1326 * ARG2: data word 1
1327 * ARG3: data word 2
1328 * ARG4: data word 3
1329 * RET0: status
1330 * ERRORS: EINVAL No trap trace buffer currently defined
1331 *
1332 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1333 * is modified - none of the other registers holding arguments are
1334 * volatile across this hypervisor service.
1335 */
1336
1337/* Core dump services.
1338 *
1339 * Since the hypervisor viraulizes and thus obscures a lot of the
1340 * physical machine layout and state, traditional OS crash dumps can
1341 * be difficult to diagnose especially when the problem is a
1342 * configuration error of some sort.
1343 *
1344 * The dump services provide an opaque buffer into which the
1345 * hypervisor can place it's internal state in order to assist in
1346 * debugging such situations. The contents are opaque and extremely
1347 * platform and hypervisor implementation specific. The guest, during
1348 * a core dump, requests that the hypervisor update any information in
1349 * the dump buffer in preparation to being dumped as part of the
1350 * domain's memory image.
1351 */
1352
1353/* dump_buf_update()
1354 * TRAP: HV_FAST_TRAP
1355 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1356 * ARG0: real address
1357 * ARG1: size
1358 * RET0: status
1359 * RET1: required size of dump buffer
1360 * ERRORS: ENORADDR Invalid real address
1361 * EBADALIGN Real address is not aligned on a 64-byte
1362 * boundary
1363 * EINVAL Size is non-zero but less than minimum size
1364 * required
1365 * ENOTSUPPORTED Operation not supported on current logical
1366 * domain
1367 *
1368 * Declare a domain dump buffer to the hypervisor. The real address
1369 * provided for the domain dump buffer must be 64-byte aligned. The
1370 * size specifies the size of the dump buffer and may be larger than
1371 * the minimum size specified in the machine description. The
1372 * hypervisor will fill the dump buffer with opaque data.
1373 *
1374 * Note: A guest may elect to include dump buffer contents as part of a crash
1375 * dump to assist with debugging. This function may be called any number
1376 * of times so that a guest may relocate a dump buffer, or create
1377 * "snapshots" of any dump-buffer information. Each call to
1378 * dump_buf_update() atomically declares the new dump buffer to the
1379 * hypervisor.
1380 *
1381 * A specified size of 0 unconfigures the dump buffer. If the real
1382 * address is illegal or badly aligned, then any currently active dump
1383 * buffer is disabled and an error is returned.
1384 *
1385 * In the event that the call fails with EINVAL, RET1 contains the
1386 * minimum size requires by the hypervisor for a valid dump buffer.
1387 */
1388#define HV_FAST_DUMP_BUF_UPDATE 0x94
1389
1390/* dump_buf_info()
1391 * TRAP: HV_FAST_TRAP
1392 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1393 * RET0: status
1394 * RET1: real address of current dump buffer
1395 * RET2: size of current dump buffer
1396 * ERRORS: No errors defined.
1397 *
1398 * Return the currently configures dump buffer description. A
1399 * returned size of 0 bytes indicates an undefined dump buffer. In
1400 * this case the return address in RET1 is undefined.
1401 */
1402#define HV_FAST_DUMP_BUF_INFO 0x95
1403
1404/* Device interrupt services.
1405 *
1406 * Device interrupts are allocated to system bus bridges by the hypervisor,
1407 * and described to OBP in the machine description. OBP then describes
1408 * these interrupts to the OS via properties in the device tree.
1409 *
1410 * Terminology:
1411 *
1412 * cpuid Unique opaque value which represents a target cpu.
1413 *
1414 * devhandle Device handle. It uniquely identifies a device, and
1415 * consistes of the lower 28-bits of the hi-cell of the
1416 * first entry of the device's "reg" property in the
1417 * OBP device tree.
1418 *
1419 * devino Device interrupt number. Specifies the relative
1420 * interrupt number within the device. The unique
1421 * combination of devhandle and devino are used to
1422 * identify a specific device interrupt.
1423 *
1424 * Note: The devino value is the same as the values in the
1425 * "interrupts" property or "interrupt-map" property
1426 * in the OBP device tree for that device.
1427 *
1428 * sysino System interrupt number. A 64-bit unsigned interger
1429 * representing a unique interrupt within a virtual
1430 * machine.
1431 *
1432 * intr_state A flag representing the interrupt state for a given
1433 * sysino. The state values are defined below.
1434 *
1435 * intr_enabled A flag representing the 'enabled' state for a given
1436 * sysino. The enable values are defined below.
1437 */
1438
1439#define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1440#define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1441#define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1442
1443#define HV_INTR_DISABLED 0 /* sysino not enabled */
1444#define HV_INTR_ENABLED 1 /* sysino enabled */
1445
1446/* intr_devino_to_sysino()
1447 * TRAP: HV_FAST_TRAP
1448 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1449 * ARG0: devhandle
1450 * ARG1: devino
1451 * RET0: status
1452 * RET1: sysino
1453 * ERRORS: EINVAL Invalid devhandle/devino
1454 *
1455 * Converts a device specific interrupt number of the given
1456 * devhandle/devino into a system specific ino (sysino).
1457 */
1458#define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1459
1460#ifndef __ASSEMBLY__
1461extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1462 unsigned long devino);
1463#endif
1464
1465/* intr_getenabled()
1466 * TRAP: HV_FAST_TRAP
1467 * FUNCTION: HV_FAST_INTR_GETENABLED
1468 * ARG0: sysino
1469 * RET0: status
1470 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1471 * ERRORS: EINVAL Invalid sysino
1472 *
1473 * Returns interrupt enabled state in RET1 for the interrupt defined
1474 * by the given sysino.
1475 */
1476#define HV_FAST_INTR_GETENABLED 0xa1
1477
1478#ifndef __ASSEMBLY__
1479extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
1480#endif
1481
1482/* intr_setenabled()
1483 * TRAP: HV_FAST_TRAP
1484 * FUNCTION: HV_FAST_INTR_SETENABLED
1485 * ARG0: sysino
1486 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1487 * RET0: status
1488 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1489 *
1490 * Set the 'enabled' state of the interrupt sysino.
1491 */
1492#define HV_FAST_INTR_SETENABLED 0xa2
1493
1494#ifndef __ASSEMBLY__
1495extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
1496#endif
1497
1498/* intr_getstate()
1499 * TRAP: HV_FAST_TRAP
1500 * FUNCTION: HV_FAST_INTR_GETSTATE
1501 * ARG0: sysino
1502 * RET0: status
1503 * RET1: intr_state (HV_INTR_STATE_*)
1504 * ERRORS: EINVAL Invalid sysino
1505 *
1506 * Returns current state of the interrupt defined by the given sysino.
1507 */
1508#define HV_FAST_INTR_GETSTATE 0xa3
1509
1510#ifndef __ASSEMBLY__
1511extern unsigned long sun4v_intr_getstate(unsigned long sysino);
1512#endif
1513
1514/* intr_setstate()
1515 * TRAP: HV_FAST_TRAP
1516 * FUNCTION: HV_FAST_INTR_SETSTATE
1517 * ARG0: sysino
1518 * ARG1: intr_state (HV_INTR_STATE_*)
1519 * RET0: status
1520 * ERRORS: EINVAL Invalid sysino or intr_state value
1521 *
1522 * Sets the current state of the interrupt described by the given sysino
1523 * value.
1524 *
1525 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1526 * interrupt for sysino.
1527 */
1528#define HV_FAST_INTR_SETSTATE 0xa4
1529
1530#ifndef __ASSEMBLY__
1531extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1532#endif
1533
1534/* intr_gettarget()
1535 * TRAP: HV_FAST_TRAP
1536 * FUNCTION: HV_FAST_INTR_GETTARGET
1537 * ARG0: sysino
1538 * RET0: status
1539 * RET1: cpuid
1540 * ERRORS: EINVAL Invalid sysino
1541 *
1542 * Returns CPU that is the current target of the interrupt defined by
1543 * the given sysino. The CPU value returned is undefined if the target
1544 * has not been set via intr_settarget().
1545 */
1546#define HV_FAST_INTR_GETTARGET 0xa5
1547
1548#ifndef __ASSEMBLY__
1549extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
1550#endif
1551
1552/* intr_settarget()
1553 * TRAP: HV_FAST_TRAP
1554 * FUNCTION: HV_FAST_INTR_SETTARGET
1555 * ARG0: sysino
1556 * ARG1: cpuid
1557 * RET0: status
1558 * ERRORS: EINVAL Invalid sysino
1559 * ENOCPU Invalid cpuid
1560 *
1561 * Set the target CPU for the interrupt defined by the given sysino.
1562 */
1563#define HV_FAST_INTR_SETTARGET 0xa6
1564
1565#ifndef __ASSEMBLY__
1566extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1567#endif
1568
1569/* vintr_get_cookie()
1570 * TRAP: HV_FAST_TRAP
1571 * FUNCTION: HV_FAST_VINTR_GET_COOKIE
1572 * ARG0: device handle
1573 * ARG1: device ino
1574 * RET0: status
1575 * RET1: cookie
1576 */
1577#define HV_FAST_VINTR_GET_COOKIE 0xa7
1578
1579/* vintr_set_cookie()
1580 * TRAP: HV_FAST_TRAP
1581 * FUNCTION: HV_FAST_VINTR_SET_COOKIE
1582 * ARG0: device handle
1583 * ARG1: device ino
1584 * ARG2: cookie
1585 * RET0: status
1586 */
1587#define HV_FAST_VINTR_SET_COOKIE 0xa8
1588
1589/* vintr_get_valid()
1590 * TRAP: HV_FAST_TRAP
1591 * FUNCTION: HV_FAST_VINTR_GET_VALID
1592 * ARG0: device handle
1593 * ARG1: device ino
1594 * RET0: status
1595 * RET1: valid state
1596 */
1597#define HV_FAST_VINTR_GET_VALID 0xa9
1598
1599/* vintr_set_valid()
1600 * TRAP: HV_FAST_TRAP
1601 * FUNCTION: HV_FAST_VINTR_SET_VALID
1602 * ARG0: device handle
1603 * ARG1: device ino
1604 * ARG2: valid state
1605 * RET0: status
1606 */
1607#define HV_FAST_VINTR_SET_VALID 0xaa
1608
1609/* vintr_get_state()
1610 * TRAP: HV_FAST_TRAP
1611 * FUNCTION: HV_FAST_VINTR_GET_STATE
1612 * ARG0: device handle
1613 * ARG1: device ino
1614 * RET0: status
1615 * RET1: state
1616 */
1617#define HV_FAST_VINTR_GET_STATE 0xab
1618
1619/* vintr_set_state()
1620 * TRAP: HV_FAST_TRAP
1621 * FUNCTION: HV_FAST_VINTR_SET_STATE
1622 * ARG0: device handle
1623 * ARG1: device ino
1624 * ARG2: state
1625 * RET0: status
1626 */
1627#define HV_FAST_VINTR_SET_STATE 0xac
1628
1629/* vintr_get_target()
1630 * TRAP: HV_FAST_TRAP
1631 * FUNCTION: HV_FAST_VINTR_GET_TARGET
1632 * ARG0: device handle
1633 * ARG1: device ino
1634 * RET0: status
1635 * RET1: cpuid
1636 */
1637#define HV_FAST_VINTR_GET_TARGET 0xad
1638
1639/* vintr_set_target()
1640 * TRAP: HV_FAST_TRAP
1641 * FUNCTION: HV_FAST_VINTR_SET_TARGET
1642 * ARG0: device handle
1643 * ARG1: device ino
1644 * ARG2: cpuid
1645 * RET0: status
1646 */
1647#define HV_FAST_VINTR_SET_TARGET 0xae
1648
1649#ifndef __ASSEMBLY__
1650extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1651 unsigned long dev_ino,
1652 unsigned long *cookie);
1653extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1654 unsigned long dev_ino,
1655 unsigned long cookie);
1656extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1657 unsigned long dev_ino,
1658 unsigned long *valid);
1659extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1660 unsigned long dev_ino,
1661 unsigned long valid);
1662extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1663 unsigned long dev_ino,
1664 unsigned long *state);
1665extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1666 unsigned long dev_ino,
1667 unsigned long state);
1668extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1669 unsigned long dev_ino,
1670 unsigned long *cpuid);
1671extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1672 unsigned long dev_ino,
1673 unsigned long cpuid);
1674#endif
1675
1676/* PCI IO services.
1677 *
1678 * See the terminology descriptions in the device interrupt services
1679 * section above as those apply here too. Here are terminology
1680 * definitions specific to these PCI IO services:
1681 *
1682 * tsbnum TSB number. Indentifies which io-tsb is used.
1683 * For this version of the specification, tsbnum
1684 * must be zero.
1685 *
1686 * tsbindex TSB index. Identifies which entry in the TSB
1687 * is used. The first entry is zero.
1688 *
1689 * tsbid A 64-bit aligned data structure which contains
1690 * a tsbnum and a tsbindex. Bits 63:32 contain the
1691 * tsbnum and bits 31:00 contain the tsbindex.
1692 *
1693 * Use the HV_PCI_TSBID() macro to construct such
1694 * values.
1695 *
1696 * io_attributes IO attributes for IOMMU mappings. One of more
1697 * of the attritbute bits are stores in a 64-bit
1698 * value. The values are defined below.
1699 *
1700 * r_addr 64-bit real address
1701 *
1702 * pci_device PCI device address. A PCI device address identifies
1703 * a specific device on a specific PCI bus segment.
1704 * A PCI device address ia a 32-bit unsigned integer
1705 * with the following format:
1706 *
1707 * 00000000.bbbbbbbb.dddddfff.00000000
1708 *
1709 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1710 * such values.
1711 *
1712 * pci_config_offset
1713 * PCI configureation space offset. For conventional
1714 * PCI a value between 0 and 255. For extended
1715 * configuration space, a value between 0 and 4095.
1716 *
1717 * Note: For PCI configuration space accesses, the offset
1718 * must be aligned to the access size.
1719 *
1720 * error_flag A return value which specifies if the action succeeded
1721 * or failed. 0 means no error, non-0 means some error
1722 * occurred while performing the service.
1723 *
1724 * io_sync_direction
1725 * Direction definition for pci_dma_sync(), defined
1726 * below in HV_PCI_SYNC_*.
1727 *
1728 * io_page_list A list of io_page_addresses, an io_page_address is
1729 * a real address.
1730 *
1731 * io_page_list_p A pointer to an io_page_list.
1732 *
1733 * "size based byte swap" - Some functions do size based byte swapping
1734 * which allows sw to access pointers and
1735 * counters in native form when the processor
1736 * operates in a different endianness than the
1737 * IO bus. Size-based byte swapping converts a
1738 * multi-byte field between big-endian and
1739 * little-endian format.
1740 */
1741
1742#define HV_PCI_MAP_ATTR_READ 0x01
1743#define HV_PCI_MAP_ATTR_WRITE 0x02
1744
1745#define HV_PCI_DEVICE_BUILD(b,d,f) \
1746 ((((b) & 0xff) << 16) | \
1747 (((d) & 0x1f) << 11) | \
1748 (((f) & 0x07) << 8))
1749
1750#define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1751 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1752
1753#define HV_PCI_SYNC_FOR_DEVICE 0x01
1754#define HV_PCI_SYNC_FOR_CPU 0x02
1755
1756/* pci_iommu_map()
1757 * TRAP: HV_FAST_TRAP
1758 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1759 * ARG0: devhandle
1760 * ARG1: tsbid
1761 * ARG2: #ttes
1762 * ARG3: io_attributes
1763 * ARG4: io_page_list_p
1764 * RET0: status
1765 * RET1: #ttes mapped
1766 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1767 * EBADALIGN Improperly aligned real address
1768 * ENORADDR Invalid real address
1769 *
1770 * Create IOMMU mappings in the sun4v device defined by the given
1771 * devhandle. The mappings are created in the TSB defined by the
1772 * tsbnum component of the given tsbid. The first mapping is created
1773 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1774 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1775 * the second at tsbnum, tsbindex + 1, etc.
1776 *
1777 * All mappings are created with the attributes defined by the io_attributes
1778 * argument. The page mapping addresses are described in the io_page_list
1779 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1780 * The first entry in the io_page_list is the address for the first iotte, the
1781 * 2nd for the 2nd iotte, and so on.
1782 *
1783 * Each io_page_address in the io_page_list must be appropriately aligned.
1784 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1785 * component of the given tsbid must be zero.
1786 *
1787 * Returns the actual number of mappings creates, which may be less than
1788 * or equal to the argument #ttes. If the function returns a value which
1789 * is less than the #ttes, the caller may continus to call the function with
1790 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1791 * mapped.
1792 *
1793 * Note: This function does not imply an iotte cache flush. The guest must
1794 * demap an entry before re-mapping it.
1795 */
1796#define HV_FAST_PCI_IOMMU_MAP 0xb0
1797
1798/* pci_iommu_demap()
1799 * TRAP: HV_FAST_TRAP
1800 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1801 * ARG0: devhandle
1802 * ARG1: tsbid
1803 * ARG2: #ttes
1804 * RET0: status
1805 * RET1: #ttes demapped
1806 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1807 *
1808 * Demap and flush IOMMU mappings in the device defined by the given
1809 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1810 * component of the given tsbid, starting at the TSB index defined by the
1811 * tsbindex component of the given tsbid.
1812 *
1813 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1814 * #ttes must be greater than zero.
1815 *
1816 * Returns the actual number of ttes demapped, which may be less than or equal
1817 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1818 * may continue to call this function with updated tsbid and #ttes arguments
1819 * until all pages are demapped.
1820 *
1821 * Note: Entries do not have to be mapped to be demapped. A demap of an
1822 * unmapped page will flush the entry from the tte cache.
1823 */
1824#define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1825
1826/* pci_iommu_getmap()
1827 * TRAP: HV_FAST_TRAP
1828 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1829 * ARG0: devhandle
1830 * ARG1: tsbid
1831 * RET0: status
1832 * RET1: io_attributes
1833 * RET2: real address
1834 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1835 * ENOMAP Mapping is not valid, no translation exists
1836 *
1837 * Read and return the mapping in the device described by the given devhandle
1838 * and tsbid. If successful, the io_attributes shall be returned in RET1
1839 * and the page address of the mapping shall be returned in RET2.
1840 *
1841 * For this version of the spec, the tsbnum component of the given tsbid
1842 * must be zero.
1843 */
1844#define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1845
1846/* pci_iommu_getbypass()
1847 * TRAP: HV_FAST_TRAP
1848 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1849 * ARG0: devhandle
1850 * ARG1: real address
1851 * ARG2: io_attributes
1852 * RET0: status
1853 * RET1: io_addr
1854 * ERRORS: EINVAL Invalid devhandle/io_attributes
1855 * ENORADDR Invalid real address
1856 * ENOTSUPPORTED Function not supported in this implementation.
1857 *
1858 * Create a "special" mapping in the device described by the given devhandle,
1859 * for the given real address and attributes. Return the IO address in RET1
1860 * if successful.
1861 */
1862#define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1863
1864/* pci_config_get()
1865 * TRAP: HV_FAST_TRAP
1866 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1867 * ARG0: devhandle
1868 * ARG1: pci_device
1869 * ARG2: pci_config_offset
1870 * ARG3: size
1871 * RET0: status
1872 * RET1: error_flag
1873 * RET2: data
1874 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1875 * EBADALIGN pci_config_offset not size aligned
1876 * ENOACCESS Access to this offset is not permitted
1877 *
1878 * Read PCI configuration space for the adapter described by the given
1879 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1880 * pci_device, at pci_config_offset from the beginning of the device's
1881 * configuration space. If there was no error, RET1 is set to zero and
1882 * RET2 is set to the data read. Insignificant bits in RET2 are not
1883 * guarenteed to have any specific value and therefore must be ignored.
1884 *
1885 * The data returned in RET2 is size based byte swapped.
1886 *
1887 * If an error occurs during the read, set RET1 to a non-zero value. The
1888 * given pci_config_offset must be 'size' aligned.
1889 */
1890#define HV_FAST_PCI_CONFIG_GET 0xb4
1891
1892/* pci_config_put()
1893 * TRAP: HV_FAST_TRAP
1894 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1895 * ARG0: devhandle
1896 * ARG1: pci_device
1897 * ARG2: pci_config_offset
1898 * ARG3: size
1899 * ARG4: data
1900 * RET0: status
1901 * RET1: error_flag
1902 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1903 * EBADALIGN pci_config_offset not size aligned
1904 * ENOACCESS Access to this offset is not permitted
1905 *
1906 * Write PCI configuration space for the adapter described by the given
1907 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1908 * at pci_config_offset from the beginning of the device's configuration
1909 * space. The data argument contains the data to be written to configuration
1910 * space. Prior to writing, the data is size based byte swapped.
1911 *
1912 * If an error occurs during the write access, do not generate an error
1913 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1914 * The given pci_config_offset must be 'size' aligned.
1915 *
1916 * This function is permitted to read from offset zero in the configuration
1917 * space described by the given pci_device if necessary to ensure that the
1918 * write access to config space completes.
1919 */
1920#define HV_FAST_PCI_CONFIG_PUT 0xb5
1921
1922/* pci_peek()
1923 * TRAP: HV_FAST_TRAP
1924 * FUNCTION: HV_FAST_PCI_PEEK
1925 * ARG0: devhandle
1926 * ARG1: real address
1927 * ARG2: size
1928 * RET0: status
1929 * RET1: error_flag
1930 * RET2: data
1931 * ERRORS: EINVAL Invalid devhandle or size
1932 * EBADALIGN Improperly aligned real address
1933 * ENORADDR Bad real address
1934 * ENOACCESS Guest access prohibited
1935 *
1936 * Attempt to read the IO address given by the given devhandle, real address,
1937 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1938 * access operation using the given size. If an error occurs when reading
1939 * from the given location, do not generate an error report, but return a
1940 * non-zero value in RET1. If the read was successful, return zero in RET1
1941 * and return the actual data read in RET2. The data returned is size based
1942 * byte swapped.
1943 *
1944 * Non-significant bits in RET2 are not guarenteed to have any specific value
1945 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1946 * value is not guarenteed to have any specific value and should be ignored.
1947 *
1948 * The caller must have permission to read from the given devhandle, real
1949 * address, which must be an IO address. The argument real address must be a
1950 * size aligned address.
1951 *
1952 * The hypervisor implementation of this function must block access to any
1953 * IO address that the guest does not have explicit permission to access.
1954 */
1955#define HV_FAST_PCI_PEEK 0xb6
1956
1957/* pci_poke()
1958 * TRAP: HV_FAST_TRAP
1959 * FUNCTION: HV_FAST_PCI_POKE
1960 * ARG0: devhandle
1961 * ARG1: real address
1962 * ARG2: size
1963 * ARG3: data
1964 * ARG4: pci_device
1965 * RET0: status
1966 * RET1: error_flag
1967 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1968 * EBADALIGN Improperly aligned real address
1969 * ENORADDR Bad real address
1970 * ENOACCESS Guest access prohibited
1971 * ENOTSUPPORTED Function is not supported by implementation
1972 *
1973 * Attempt to write data to the IO address given by the given devhandle,
1974 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1975 * performed as a single access operation using the given size. Prior to
1976 * writing the data is size based swapped.
1977 *
1978 * If an error occurs when writing to the given location, do not generate an
1979 * error report, but return a non-zero value in RET1. If the write was
1980 * successful, return zero in RET1.
1981 *
1982 * pci_device describes the configuration address of the device being
1983 * written to. The implementation may safely read from offset 0 with
1984 * the configuration space of the device described by devhandle and
1985 * pci_device in order to guarantee that the write portion of the operation
1986 * completes
1987 *
1988 * Any error that occurs due to the read shall be reported using the normal
1989 * error reporting mechanisms .. the read error is not suppressed.
1990 *
1991 * The caller must have permission to write to the given devhandle, real
1992 * address, which must be an IO address. The argument real address must be a
1993 * size aligned address. The caller must have permission to read from
1994 * the given devhandle, pci_device cofiguration space offset 0.
1995 *
1996 * The hypervisor implementation of this function must block access to any
1997 * IO address that the guest does not have explicit permission to access.
1998 */
1999#define HV_FAST_PCI_POKE 0xb7
2000
2001/* pci_dma_sync()
2002 * TRAP: HV_FAST_TRAP
2003 * FUNCTION: HV_FAST_PCI_DMA_SYNC
2004 * ARG0: devhandle
2005 * ARG1: real address
2006 * ARG2: size
2007 * ARG3: io_sync_direction
2008 * RET0: status
2009 * RET1: #synced
2010 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
2011 * ENORADDR Bad real address
2012 *
2013 * Synchronize a memory region described by the given real address and size,
2014 * for the device defined by the given devhandle using the direction(s)
2015 * defined by the given io_sync_direction. The argument size is the size of
2016 * the memory region in bytes.
2017 *
2018 * Return the actual number of bytes synchronized in the return value #synced,
2019 * which may be less than or equal to the argument size. If the return
2020 * value #synced is less than size, the caller must continue to call this
2021 * function with updated real address and size arguments until the entire
2022 * memory region is synchronized.
2023 */
2024#define HV_FAST_PCI_DMA_SYNC 0xb8
2025
2026/* PCI MSI services. */
2027
2028#define HV_MSITYPE_MSI32 0x00
2029#define HV_MSITYPE_MSI64 0x01
2030
2031#define HV_MSIQSTATE_IDLE 0x00
2032#define HV_MSIQSTATE_ERROR 0x01
2033
2034#define HV_MSIQ_INVALID 0x00
2035#define HV_MSIQ_VALID 0x01
2036
2037#define HV_MSISTATE_IDLE 0x00
2038#define HV_MSISTATE_DELIVERED 0x01
2039
2040#define HV_MSIVALID_INVALID 0x00
2041#define HV_MSIVALID_VALID 0x01
2042
2043#define HV_PCIE_MSGTYPE_PME_MSG 0x18
2044#define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
2045#define HV_PCIE_MSGTYPE_CORR_MSG 0x30
2046#define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
2047#define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
2048
2049#define HV_MSG_INVALID 0x00
2050#define HV_MSG_VALID 0x01
2051
2052/* pci_msiq_conf()
2053 * TRAP: HV_FAST_TRAP
2054 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
2055 * ARG0: devhandle
2056 * ARG1: msiqid
2057 * ARG2: real address
2058 * ARG3: number of entries
2059 * RET0: status
2060 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
2061 * EBADALIGN Improperly aligned real address
2062 * ENORADDR Bad real address
2063 *
2064 * Configure the MSI queue given by the devhandle and msiqid arguments,
2065 * and to be placed at the given real address and be of the given
2066 * number of entries. The real address must be aligned exactly to match
2067 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
2068 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
2069 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2070 *
2071 * Implementation Note: Certain implementations have fixed sized queues. In
2072 * that case, number of entries must contain the correct
2073 * value.
2074 */
2075#define HV_FAST_PCI_MSIQ_CONF 0xc0
2076
2077/* pci_msiq_info()
2078 * TRAP: HV_FAST_TRAP
2079 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
2080 * ARG0: devhandle
2081 * ARG1: msiqid
2082 * RET0: status
2083 * RET1: real address
2084 * RET2: number of entries
2085 * ERRORS: EINVAL Invalid devhandle or msiqid
2086 *
2087 * Return the configuration information for the MSI queue described
2088 * by the given devhandle and msiqid. The base address of the queue
2089 * is returned in ARG1 and the number of entries is returned in ARG2.
2090 * If the queue is unconfigured, the real address is undefined and the
2091 * number of entries will be returned as zero.
2092 */
2093#define HV_FAST_PCI_MSIQ_INFO 0xc1
2094
2095/* pci_msiq_getvalid()
2096 * TRAP: HV_FAST_TRAP
2097 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2098 * ARG0: devhandle
2099 * ARG1: msiqid
2100 * RET0: status
2101 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2102 * ERRORS: EINVAL Invalid devhandle or msiqid
2103 *
2104 * Get the valid state of the MSI-EQ described by the given devhandle and
2105 * msiqid.
2106 */
2107#define HV_FAST_PCI_MSIQ_GETVALID 0xc2
2108
2109/* pci_msiq_setvalid()
2110 * TRAP: HV_FAST_TRAP
2111 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
2112 * ARG0: devhandle
2113 * ARG1: msiqid
2114 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2115 * RET0: status
2116 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
2117 * value or MSI EQ is uninitialized
2118 *
2119 * Set the valid state of the MSI-EQ described by the given devhandle and
2120 * msiqid to the given msiqvalid.
2121 */
2122#define HV_FAST_PCI_MSIQ_SETVALID 0xc3
2123
2124/* pci_msiq_getstate()
2125 * TRAP: HV_FAST_TRAP
2126 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
2127 * ARG0: devhandle
2128 * ARG1: msiqid
2129 * RET0: status
2130 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2131 * ERRORS: EINVAL Invalid devhandle or msiqid
2132 *
2133 * Get the state of the MSI-EQ described by the given devhandle and
2134 * msiqid.
2135 */
2136#define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
2137
2138/* pci_msiq_getvalid()
2139 * TRAP: HV_FAST_TRAP
2140 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2141 * ARG0: devhandle
2142 * ARG1: msiqid
2143 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2144 * RET0: status
2145 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
2146 * value or MSI EQ is uninitialized
2147 *
2148 * Set the state of the MSI-EQ described by the given devhandle and
2149 * msiqid to the given msiqvalid.
2150 */
2151#define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
2152
2153/* pci_msiq_gethead()
2154 * TRAP: HV_FAST_TRAP
2155 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
2156 * ARG0: devhandle
2157 * ARG1: msiqid
2158 * RET0: status
2159 * RET1: msiqhead
2160 * ERRORS: EINVAL Invalid devhandle or msiqid
2161 *
2162 * Get the current MSI EQ queue head for the MSI-EQ described by the
2163 * given devhandle and msiqid.
2164 */
2165#define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
2166
2167/* pci_msiq_sethead()
2168 * TRAP: HV_FAST_TRAP
2169 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
2170 * ARG0: devhandle
2171 * ARG1: msiqid
2172 * ARG2: msiqhead
2173 * RET0: status
2174 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
2175 * or MSI EQ is uninitialized
2176 *
2177 * Set the current MSI EQ queue head for the MSI-EQ described by the
2178 * given devhandle and msiqid.
2179 */
2180#define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
2181
2182/* pci_msiq_gettail()
2183 * TRAP: HV_FAST_TRAP
2184 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
2185 * ARG0: devhandle
2186 * ARG1: msiqid
2187 * RET0: status
2188 * RET1: msiqtail
2189 * ERRORS: EINVAL Invalid devhandle or msiqid
2190 *
2191 * Get the current MSI EQ queue tail for the MSI-EQ described by the
2192 * given devhandle and msiqid.
2193 */
2194#define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
2195
2196/* pci_msi_getvalid()
2197 * TRAP: HV_FAST_TRAP
2198 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
2199 * ARG0: devhandle
2200 * ARG1: msinum
2201 * RET0: status
2202 * RET1: msivalidstate
2203 * ERRORS: EINVAL Invalid devhandle or msinum
2204 *
2205 * Get the current valid/enabled state for the MSI defined by the
2206 * given devhandle and msinum.
2207 */
2208#define HV_FAST_PCI_MSI_GETVALID 0xc9
2209
2210/* pci_msi_setvalid()
2211 * TRAP: HV_FAST_TRAP
2212 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
2213 * ARG0: devhandle
2214 * ARG1: msinum
2215 * ARG2: msivalidstate
2216 * RET0: status
2217 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
2218 *
2219 * Set the current valid/enabled state for the MSI defined by the
2220 * given devhandle and msinum.
2221 */
2222#define HV_FAST_PCI_MSI_SETVALID 0xca
2223
2224/* pci_msi_getmsiq()
2225 * TRAP: HV_FAST_TRAP
2226 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
2227 * ARG0: devhandle
2228 * ARG1: msinum
2229 * RET0: status
2230 * RET1: msiqid
2231 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
2232 *
2233 * Get the MSI EQ that the MSI defined by the given devhandle and
2234 * msinum is bound to.
2235 */
2236#define HV_FAST_PCI_MSI_GETMSIQ 0xcb
2237
2238/* pci_msi_setmsiq()
2239 * TRAP: HV_FAST_TRAP
2240 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
2241 * ARG0: devhandle
2242 * ARG1: msinum
2243 * ARG2: msitype
2244 * ARG3: msiqid
2245 * RET0: status
2246 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
2247 *
2248 * Set the MSI EQ that the MSI defined by the given devhandle and
2249 * msinum is bound to.
2250 */
2251#define HV_FAST_PCI_MSI_SETMSIQ 0xcc
2252
2253/* pci_msi_getstate()
2254 * TRAP: HV_FAST_TRAP
2255 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
2256 * ARG0: devhandle
2257 * ARG1: msinum
2258 * RET0: status
2259 * RET1: msistate
2260 * ERRORS: EINVAL Invalid devhandle or msinum
2261 *
2262 * Get the state of the MSI defined by the given devhandle and msinum.
2263 * If not initialized, return HV_MSISTATE_IDLE.
2264 */
2265#define HV_FAST_PCI_MSI_GETSTATE 0xcd
2266
2267/* pci_msi_setstate()
2268 * TRAP: HV_FAST_TRAP
2269 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
2270 * ARG0: devhandle
2271 * ARG1: msinum
2272 * ARG2: msistate
2273 * RET0: status
2274 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
2275 *
2276 * Set the state of the MSI defined by the given devhandle and msinum.
2277 */
2278#define HV_FAST_PCI_MSI_SETSTATE 0xce
2279
2280/* pci_msg_getmsiq()
2281 * TRAP: HV_FAST_TRAP
2282 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
2283 * ARG0: devhandle
2284 * ARG1: msgtype
2285 * RET0: status
2286 * RET1: msiqid
2287 * ERRORS: EINVAL Invalid devhandle or msgtype
2288 *
2289 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2290 */
2291#define HV_FAST_PCI_MSG_GETMSIQ 0xd0
2292
2293/* pci_msg_setmsiq()
2294 * TRAP: HV_FAST_TRAP
2295 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
2296 * ARG0: devhandle
2297 * ARG1: msgtype
2298 * ARG2: msiqid
2299 * RET0: status
2300 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
2301 *
2302 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2303 */
2304#define HV_FAST_PCI_MSG_SETMSIQ 0xd1
2305
2306/* pci_msg_getvalid()
2307 * TRAP: HV_FAST_TRAP
2308 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
2309 * ARG0: devhandle
2310 * ARG1: msgtype
2311 * RET0: status
2312 * RET1: msgvalidstate
2313 * ERRORS: EINVAL Invalid devhandle or msgtype
2314 *
2315 * Get the valid/enabled state of the MSG defined by the given
2316 * devhandle and msgtype.
2317 */
2318#define HV_FAST_PCI_MSG_GETVALID 0xd2
2319
2320/* pci_msg_setvalid()
2321 * TRAP: HV_FAST_TRAP
2322 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
2323 * ARG0: devhandle
2324 * ARG1: msgtype
2325 * ARG2: msgvalidstate
2326 * RET0: status
2327 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
2328 *
2329 * Set the valid/enabled state of the MSG defined by the given
2330 * devhandle and msgtype.
2331 */
2332#define HV_FAST_PCI_MSG_SETVALID 0xd3
2333
2334/* Logical Domain Channel services. */
2335
2336#define LDC_CHANNEL_DOWN 0
2337#define LDC_CHANNEL_UP 1
2338#define LDC_CHANNEL_RESETTING 2
2339
2340/* ldc_tx_qconf()
2341 * TRAP: HV_FAST_TRAP
2342 * FUNCTION: HV_FAST_LDC_TX_QCONF
2343 * ARG0: channel ID
2344 * ARG1: real address base of queue
2345 * ARG2: num entries in queue
2346 * RET0: status
2347 *
2348 * Configure transmit queue for the LDC endpoint specified by the
2349 * given channel ID, to be placed at the given real address, and
2350 * be of the given num entries. Num entries must be a power of two.
2351 * The real address base of the queue must be aligned on the queue
2352 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2353 * queue must be aligned on a 2048 byte real address boundary.
2354 *
2355 * Upon configuration of a valid transmit queue the head and tail
2356 * pointers are set to a hypervisor specific identical value indicating
2357 * that the queue initially is empty.
2358 *
2359 * The endpoint's transmit queue is un-configured if num entries is zero.
2360 *
2361 * The maximum number of entries for each queue for a specific cpu may be
2362 * determined from the machine description. A transmit queue may be
2363 * specified even in the event that the LDC is down (peer endpoint has no
2364 * receive queue specified). Transmission will begin as soon as the peer
2365 * endpoint defines a receive queue.
2366 *
2367 * It is recommended that a guest wait for a transmit queue to empty prior
2368 * to reconfiguring it, or un-configuring it. Re or un-configuring of a
2369 * non-empty transmit queue behaves exactly as defined above, however it
2370 * is undefined as to how many of the pending entries in the original queue
2371 * will be delivered prior to the re-configuration taking effect.
2372 * Furthermore, as the queue configuration causes a reset of the head and
2373 * tail pointers there is no way for a guest to determine how many entries
2374 * have been sent after the configuration operation.
2375 */
2376#define HV_FAST_LDC_TX_QCONF 0xe0
2377
2378/* ldc_tx_qinfo()
2379 * TRAP: HV_FAST_TRAP
2380 * FUNCTION: HV_FAST_LDC_TX_QINFO
2381 * ARG0: channel ID
2382 * RET0: status
2383 * RET1: real address base of queue
2384 * RET2: num entries in queue
2385 *
2386 * Return the configuration info for the transmit queue of LDC endpoint
2387 * defined by the given channel ID. The real address is the currently
2388 * defined real address base of the defined queue, and num entries is the
2389 * size of the queue in terms of number of entries.
2390 *
2391 * If the specified channel ID is a valid endpoint number, but no transmit
2392 * queue has been defined this service will return success, but with num
2393 * entries set to zero and the real address will have an undefined value.
2394 */
2395#define HV_FAST_LDC_TX_QINFO 0xe1
2396
2397/* ldc_tx_get_state()
2398 * TRAP: HV_FAST_TRAP
2399 * FUNCTION: HV_FAST_LDC_TX_GET_STATE
2400 * ARG0: channel ID
2401 * RET0: status
2402 * RET1: head offset
2403 * RET2: tail offset
2404 * RET3: channel state
2405 *
2406 * Return the transmit state, and the head and tail queue pointers, for
2407 * the transmit queue of the LDC endpoint defined by the given channel ID.
2408 * The head and tail values are the byte offset of the head and tail
2409 * positions of the transmit queue for the specified endpoint.
2410 */
2411#define HV_FAST_LDC_TX_GET_STATE 0xe2
2412
2413/* ldc_tx_set_qtail()
2414 * TRAP: HV_FAST_TRAP
2415 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
2416 * ARG0: channel ID
2417 * ARG1: tail offset
2418 * RET0: status
2419 *
2420 * Update the tail pointer for the transmit queue associated with the LDC
2421 * endpoint defined by the given channel ID. The tail offset specified
2422 * must be aligned on a 64 byte boundary, and calculated so as to increase
2423 * the number of pending entries on the transmit queue. Any attempt to
2424 * decrease the number of pending transmit queue entires is considered
2425 * an invalid tail offset and will result in an EINVAL error.
2426 *
2427 * Since the tail of the transmit queue may not be moved backwards, the
2428 * transmit queue may be flushed by configuring a new transmit queue,
2429 * whereupon the hypervisor will configure the initial transmit head and
2430 * tail pointers to be equal.
2431 */
2432#define HV_FAST_LDC_TX_SET_QTAIL 0xe3
2433
2434/* ldc_rx_qconf()
2435 * TRAP: HV_FAST_TRAP
2436 * FUNCTION: HV_FAST_LDC_RX_QCONF
2437 * ARG0: channel ID
2438 * ARG1: real address base of queue
2439 * ARG2: num entries in queue
2440 * RET0: status
2441 *
2442 * Configure receive queue for the LDC endpoint specified by the
2443 * given channel ID, to be placed at the given real address, and
2444 * be of the given num entries. Num entries must be a power of two.
2445 * The real address base of the queue must be aligned on the queue
2446 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2447 * queue must be aligned on a 2048 byte real address boundary.
2448 *
2449 * The endpoint's transmit queue is un-configured if num entries is zero.
2450 *
2451 * If a valid receive queue is specified for a local endpoint the LDC is
2452 * in the up state for the purpose of transmission to this endpoint.
2453 *
2454 * The maximum number of entries for each queue for a specific cpu may be
2455 * determined from the machine description.
2456 *
2457 * As receive queue configuration causes a reset of the queue's head and
2458 * tail pointers there is no way for a gues to determine how many entries
2459 * have been received between a preceeding ldc_get_rx_state() API call
2460 * and the completion of the configuration operation. It should be noted
2461 * that datagram delivery is not guarenteed via domain channels anyway,
2462 * and therefore any higher protocol should be resilient to datagram
2463 * loss if necessary. However, to overcome this specific race potential
2464 * it is recommended, for example, that a higher level protocol be employed
2465 * to ensure either retransmission, or ensure that no datagrams are pending
2466 * on the peer endpoint's transmit queue prior to the configuration process.
2467 */
2468#define HV_FAST_LDC_RX_QCONF 0xe4
2469
2470/* ldc_rx_qinfo()
2471 * TRAP: HV_FAST_TRAP
2472 * FUNCTION: HV_FAST_LDC_RX_QINFO
2473 * ARG0: channel ID
2474 * RET0: status
2475 * RET1: real address base of queue
2476 * RET2: num entries in queue
2477 *
2478 * Return the configuration info for the receive queue of LDC endpoint
2479 * defined by the given channel ID. The real address is the currently
2480 * defined real address base of the defined queue, and num entries is the
2481 * size of the queue in terms of number of entries.
2482 *
2483 * If the specified channel ID is a valid endpoint number, but no receive
2484 * queue has been defined this service will return success, but with num
2485 * entries set to zero and the real address will have an undefined value.
2486 */
2487#define HV_FAST_LDC_RX_QINFO 0xe5
2488
2489/* ldc_rx_get_state()
2490 * TRAP: HV_FAST_TRAP
2491 * FUNCTION: HV_FAST_LDC_RX_GET_STATE
2492 * ARG0: channel ID
2493 * RET0: status
2494 * RET1: head offset
2495 * RET2: tail offset
2496 * RET3: channel state
2497 *
2498 * Return the receive state, and the head and tail queue pointers, for
2499 * the receive queue of the LDC endpoint defined by the given channel ID.
2500 * The head and tail values are the byte offset of the head and tail
2501 * positions of the receive queue for the specified endpoint.
2502 */
2503#define HV_FAST_LDC_RX_GET_STATE 0xe6
2504
2505/* ldc_rx_set_qhead()
2506 * TRAP: HV_FAST_TRAP
2507 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
2508 * ARG0: channel ID
2509 * ARG1: head offset
2510 * RET0: status
2511 *
2512 * Update the head pointer for the receive queue associated with the LDC
2513 * endpoint defined by the given channel ID. The head offset specified
2514 * must be aligned on a 64 byte boundary, and calculated so as to decrease
2515 * the number of pending entries on the receive queue. Any attempt to
2516 * increase the number of pending receive queue entires is considered
2517 * an invalid head offset and will result in an EINVAL error.
2518 *
2519 * The receive queue may be flushed by setting the head offset equal
2520 * to the current tail offset.
2521 */
2522#define HV_FAST_LDC_RX_SET_QHEAD 0xe7
2523
2524/* LDC Map Table Entry. Each slot is defined by a translation table
2525 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
2526 * hypervisor invalidation cookie.
2527 */
2528#define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
2529#define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
2530#define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
2531#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
2532#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
2533#define LDC_MTE_EXEC 0x0000000000000040 /* execute */
2534#define LDC_MTE_WRITE 0x0000000000000020 /* read */
2535#define LDC_MTE_READ 0x0000000000000010 /* write */
2536#define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
2537#define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
2538#define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
2539#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
2540#define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
2541#define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
2542#define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
2543#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
2544#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
2545
2546#ifndef __ASSEMBLY__
2547struct ldc_mtable_entry {
2548 unsigned long mte;
2549 unsigned long cookie;
2550};
2551#endif
2552
2553/* ldc_set_map_table()
2554 * TRAP: HV_FAST_TRAP
2555 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
2556 * ARG0: channel ID
2557 * ARG1: table real address
2558 * ARG2: num entries
2559 * RET0: status
2560 *
2561 * Register the MTE table at the given table real address, with the
2562 * specified num entries, for the LDC indicated by the given channel
2563 * ID.
2564 */
2565#define HV_FAST_LDC_SET_MAP_TABLE 0xea
2566
2567/* ldc_get_map_table()
2568 * TRAP: HV_FAST_TRAP
2569 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
2570 * ARG0: channel ID
2571 * RET0: status
2572 * RET1: table real address
2573 * RET2: num entries
2574 *
2575 * Return the configuration of the current mapping table registered
2576 * for the given channel ID.
2577 */
2578#define HV_FAST_LDC_GET_MAP_TABLE 0xeb
2579
2580#define LDC_COPY_IN 0
2581#define LDC_COPY_OUT 1
2582
2583/* ldc_copy()
2584 * TRAP: HV_FAST_TRAP
2585 * FUNCTION: HV_FAST_LDC_COPY
2586 * ARG0: channel ID
2587 * ARG1: LDC_COPY_* direction code
2588 * ARG2: target real address
2589 * ARG3: local real address
2590 * ARG4: length in bytes
2591 * RET0: status
2592 * RET1: actual length in bytes
2593 */
2594#define HV_FAST_LDC_COPY 0xec
2595
2596#define LDC_MEM_READ 1
2597#define LDC_MEM_WRITE 2
2598#define LDC_MEM_EXEC 4
2599
2600/* ldc_mapin()
2601 * TRAP: HV_FAST_TRAP
2602 * FUNCTION: HV_FAST_LDC_MAPIN
2603 * ARG0: channel ID
2604 * ARG1: cookie
2605 * RET0: status
2606 * RET1: real address
2607 * RET2: LDC_MEM_* permissions
2608 */
2609#define HV_FAST_LDC_MAPIN 0xed
2610
2611/* ldc_unmap()
2612 * TRAP: HV_FAST_TRAP
2613 * FUNCTION: HV_FAST_LDC_UNMAP
2614 * ARG0: real address
2615 * RET0: status
2616 */
2617#define HV_FAST_LDC_UNMAP 0xee
2618
2619/* ldc_revoke()
2620 * TRAP: HV_FAST_TRAP
2621 * FUNCTION: HV_FAST_LDC_REVOKE
2622 * ARG0: channel ID
2623 * ARG1: cookie
2624 * ARG2: ldc_mtable_entry cookie
2625 * RET0: status
2626 */
2627#define HV_FAST_LDC_REVOKE 0xef
2628
2629#ifndef __ASSEMBLY__
2630extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
2631 unsigned long ra,
2632 unsigned long num_entries);
2633extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
2634 unsigned long *ra,
2635 unsigned long *num_entries);
2636extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
2637 unsigned long *head_off,
2638 unsigned long *tail_off,
2639 unsigned long *chan_state);
2640extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
2641 unsigned long tail_off);
2642extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
2643 unsigned long ra,
2644 unsigned long num_entries);
2645extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
2646 unsigned long *ra,
2647 unsigned long *num_entries);
2648extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
2649 unsigned long *head_off,
2650 unsigned long *tail_off,
2651 unsigned long *chan_state);
2652extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
2653 unsigned long head_off);
2654extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
2655 unsigned long ra,
2656 unsigned long num_entries);
2657extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
2658 unsigned long *ra,
2659 unsigned long *num_entries);
2660extern unsigned long sun4v_ldc_copy(unsigned long channel,
2661 unsigned long dir_code,
2662 unsigned long tgt_raddr,
2663 unsigned long lcl_raddr,
2664 unsigned long len,
2665 unsigned long *actual_len);
2666extern unsigned long sun4v_ldc_mapin(unsigned long channel,
2667 unsigned long cookie,
2668 unsigned long *ra,
2669 unsigned long *perm);
2670extern unsigned long sun4v_ldc_unmap(unsigned long ra);
2671extern unsigned long sun4v_ldc_revoke(unsigned long channel,
2672 unsigned long cookie,
2673 unsigned long mte_cookie);
2674#endif
2675
2676/* Performance counter services. */
2677
2678#define HV_PERF_JBUS_PERF_CTRL_REG 0x00
2679#define HV_PERF_JBUS_PERF_CNT_REG 0x01
2680#define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
2681#define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
2682#define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
2683#define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
2684#define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
2685#define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
2686#define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
2687#define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
2688
2689/* get_perfreg()
2690 * TRAP: HV_FAST_TRAP
2691 * FUNCTION: HV_FAST_GET_PERFREG
2692 * ARG0: performance reg number
2693 * RET0: status
2694 * RET1: performance reg value
2695 * ERRORS: EINVAL Invalid performance register number
2696 * ENOACCESS No access allowed to performance counters
2697 *
2698 * Read the value of the given DRAM/JBUS performance counter/control register.
2699 */
2700#define HV_FAST_GET_PERFREG 0x100
2701
2702/* set_perfreg()
2703 * TRAP: HV_FAST_TRAP
2704 * FUNCTION: HV_FAST_SET_PERFREG
2705 * ARG0: performance reg number
2706 * ARG1: performance reg value
2707 * RET0: status
2708 * ERRORS: EINVAL Invalid performance register number
2709 * ENOACCESS No access allowed to performance counters
2710 *
2711 * Write the given performance reg value to the given DRAM/JBUS
2712 * performance counter/control register.
2713 */
2714#define HV_FAST_SET_PERFREG 0x101
2715
2716/* MMU statistics services.
2717 *
2718 * The hypervisor maintains MMU statistics and privileged code provides
2719 * a buffer where these statistics can be collected. It is continually
2720 * updated once configured. The layout is as follows:
2721 */
2722#ifndef __ASSEMBLY__
2723struct hv_mmu_statistics {
2724 unsigned long immu_tsb_hits_ctx0_8k_tte;
2725 unsigned long immu_tsb_ticks_ctx0_8k_tte;
2726 unsigned long immu_tsb_hits_ctx0_64k_tte;
2727 unsigned long immu_tsb_ticks_ctx0_64k_tte;
2728 unsigned long __reserved1[2];
2729 unsigned long immu_tsb_hits_ctx0_4mb_tte;
2730 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
2731 unsigned long __reserved2[2];
2732 unsigned long immu_tsb_hits_ctx0_256mb_tte;
2733 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
2734 unsigned long __reserved3[4];
2735 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
2736 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
2737 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2738 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2739 unsigned long __reserved4[2];
2740 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2741 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2742 unsigned long __reserved5[2];
2743 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2744 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2745 unsigned long __reserved6[4];
2746 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2747 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2748 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2749 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2750 unsigned long __reserved7[2];
2751 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2752 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2753 unsigned long __reserved8[2];
2754 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2755 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2756 unsigned long __reserved9[4];
2757 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2758 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2759 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2760 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2761 unsigned long __reserved10[2];
2762 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2763 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2764 unsigned long __reserved11[2];
2765 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2766 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2767 unsigned long __reserved12[4];
2768};
2769#endif
2770
2771/* mmustat_conf()
2772 * TRAP: HV_FAST_TRAP
2773 * FUNCTION: HV_FAST_MMUSTAT_CONF
2774 * ARG0: real address
2775 * RET0: status
2776 * RET1: real address
2777 * ERRORS: ENORADDR Invalid real address
2778 * EBADALIGN Real address not aligned on 64-byte boundary
2779 * EBADTRAP API not supported on this processor
2780 *
2781 * Enable MMU statistic gathering using the buffer at the given real
2782 * address on the current virtual CPU. The new buffer real address
2783 * is given in ARG1, and the previously specified buffer real address
2784 * is returned in RET1, or is returned as zero for the first invocation.
2785 *
2786 * If the passed in real address argument is zero, this will disable
2787 * MMU statistic collection on the current virtual CPU. If an error is
2788 * returned then no statistics are collected.
2789 *
2790 * The buffer contents should be initialized to all zeros before being
2791 * given to the hypervisor or else the statistics will be meaningless.
2792 */
2793#define HV_FAST_MMUSTAT_CONF 0x102
2794
2795/* mmustat_info()
2796 * TRAP: HV_FAST_TRAP
2797 * FUNCTION: HV_FAST_MMUSTAT_INFO
2798 * RET0: status
2799 * RET1: real address
2800 * ERRORS: EBADTRAP API not supported on this processor
2801 *
2802 * Return the current state and real address of the currently configured
2803 * MMU statistics buffer on the current virtual CPU.
2804 */
2805#define HV_FAST_MMUSTAT_INFO 0x103
2806
2807#ifndef __ASSEMBLY__
2808extern unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
2809extern unsigned long sun4v_mmustat_info(unsigned long *ra);
2810#endif
2811
2812/* NCS crypto services */
2813
2814/* ncs_request() sub-function numbers */
2815#define HV_NCS_QCONF 0x01
2816#define HV_NCS_QTAIL_UPDATE 0x02
2817
2818#ifndef __ASSEMBLY__
2819struct hv_ncs_queue_entry {
2820 /* MAU Control Register */
2821 unsigned long mau_control;
2822#define MAU_CONTROL_INV_PARITY 0x0000000000002000
2823#define MAU_CONTROL_STRAND 0x0000000000001800
2824#define MAU_CONTROL_BUSY 0x0000000000000400
2825#define MAU_CONTROL_INT 0x0000000000000200
2826#define MAU_CONTROL_OP 0x00000000000001c0
2827#define MAU_CONTROL_OP_SHIFT 6
2828#define MAU_OP_LOAD_MA_MEMORY 0x0
2829#define MAU_OP_STORE_MA_MEMORY 0x1
2830#define MAU_OP_MODULAR_MULT 0x2
2831#define MAU_OP_MODULAR_REDUCE 0x3
2832#define MAU_OP_MODULAR_EXP_LOOP 0x4
2833#define MAU_CONTROL_LEN 0x000000000000003f
2834#define MAU_CONTROL_LEN_SHIFT 0
2835
2836 /* Real address of bytes to load or store bytes
2837 * into/out-of the MAU.
2838 */
2839 unsigned long mau_mpa;
2840
2841 /* Modular Arithmetic MA Offset Register. */
2842 unsigned long mau_ma;
2843
2844 /* Modular Arithmetic N Prime Register. */
2845 unsigned long mau_np;
2846};
2847
2848struct hv_ncs_qconf_arg {
2849 unsigned long mid; /* MAU ID, 1 per core on Niagara */
2850 unsigned long base; /* Real address base of queue */
2851 unsigned long end; /* Real address end of queue */
2852 unsigned long num_ents; /* Number of entries in queue */
2853};
2854
2855struct hv_ncs_qtail_update_arg {
2856 unsigned long mid; /* MAU ID, 1 per core on Niagara */
2857 unsigned long tail; /* New tail index to use */
2858 unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
2859#define HV_NCS_SYNCFLAG_SYNC 0x00
2860#define HV_NCS_SYNCFLAG_ASYNC 0x01
2861};
2862#endif
2863
2864/* ncs_request()
2865 * TRAP: HV_FAST_TRAP
2866 * FUNCTION: HV_FAST_NCS_REQUEST
2867 * ARG0: NCS sub-function
2868 * ARG1: sub-function argument real address
2869 * ARG2: size in bytes of sub-function argument
2870 * RET0: status
2871 *
2872 * The MAU chip of the Niagara processor is not directly accessible
2873 * to privileged code, instead it is programmed indirectly via this
2874 * hypervisor API.
2875 *
2876 * The interfaces defines a queue of MAU operations to perform.
2877 * Privileged code registers a queue with the hypervisor by invoking
2878 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
2879 * base, end, and number of entries of the queue. Each queue entry
2880 * contains a MAU register struct block.
2881 *
2882 * The privileged code then proceeds to add entries to the queue and
2883 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
2884 * synchronous operations are supported by the current hypervisor,
2885 * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
2886 * completion and return HV_EOK, or return an error code.
2887 *
2888 * The real address of the sub-function argument must be aligned on at
2889 * least an 8-byte boundary.
2890 *
2891 * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
2892 * offset, into the queue and must be less than or equal the 'num_ents'
2893 * argument given in the HV_NCS_QCONF call.
2894 */
2895#define HV_FAST_NCS_REQUEST 0x110
2896
2897#ifndef __ASSEMBLY__
2898extern unsigned long sun4v_ncs_request(unsigned long request,
2899 unsigned long arg_ra,
2900 unsigned long arg_size);
2901#endif
2902
2903#define HV_FAST_FIRE_GET_PERFREG 0x120
2904#define HV_FAST_FIRE_SET_PERFREG 0x121
2905
2906/* Function numbers for HV_CORE_TRAP. */
2907#define HV_CORE_SET_VER 0x00
2908#define HV_CORE_PUTCHAR 0x01
2909#define HV_CORE_EXIT 0x02
2910#define HV_CORE_GET_VER 0x03
2911
2912/* Hypervisor API groups for use with HV_CORE_SET_VER and
2913 * HV_CORE_GET_VER.
2914 */
2915#define HV_GRP_SUN4V 0x0000
2916#define HV_GRP_CORE 0x0001
2917#define HV_GRP_INTR 0x0002
2918#define HV_GRP_SOFT_STATE 0x0003
2919#define HV_GRP_PCI 0x0100
2920#define HV_GRP_LDOM 0x0101
2921#define HV_GRP_SVC_CHAN 0x0102
2922#define HV_GRP_NCS 0x0103
2923#define HV_GRP_NIAG_PERF 0x0200
2924#define HV_GRP_FIRE_PERF 0x0201
2925#define HV_GRP_DIAG 0x0300
2926
2927#ifndef __ASSEMBLY__
2928extern unsigned long sun4v_get_version(unsigned long group,
2929 unsigned long *major,
2930 unsigned long *minor);
2931extern unsigned long sun4v_set_version(unsigned long group,
2932 unsigned long major,
2933 unsigned long minor,
2934 unsigned long *actual_minor);
2935
2936extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
2937 unsigned long *minor);
2938extern void sun4v_hvapi_unregister(unsigned long group);
2939extern int sun4v_hvapi_get(unsigned long group,
2940 unsigned long *major,
2941 unsigned long *minor);
2942extern void sun4v_hvapi_init(void);
2943#endif
2944
2945#endif /* !(_SPARC64_HYPERVISOR_H) */
diff --git a/include/asm-sparc64/intr_queue.h b/include/asm-sparc64/intr_queue.h
index 206077dedc2a..f7225015b3db 100644
--- a/include/asm-sparc64/intr_queue.h
+++ b/include/asm-sparc64/intr_queue.h
@@ -1,15 +1 @@
1#ifndef _SPARC64_INTR_QUEUE_H #include <asm-sparc/intr_queue.h>
2#define _SPARC64_INTR_QUEUE_H
3
4/* Sun4v interrupt queue registers, accessed via ASI_QUEUE. */
5
6#define INTRQ_CPU_MONDO_HEAD 0x3c0 /* CPU mondo head */
7#define INTRQ_CPU_MONDO_TAIL 0x3c8 /* CPU mondo tail */
8#define INTRQ_DEVICE_MONDO_HEAD 0x3d0 /* Device mondo head */
9#define INTRQ_DEVICE_MONDO_TAIL 0x3d8 /* Device mondo tail */
10#define INTRQ_RESUM_MONDO_HEAD 0x3e0 /* Resumable error mondo head */
11#define INTRQ_RESUM_MONDO_TAIL 0x3e8 /* Resumable error mondo tail */
12#define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
13#define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
14
15#endif /* !(_SPARC64_INTR_QUEUE_H) */
diff --git a/include/asm-sparc64/kprobes.h b/include/asm-sparc64/kprobes.h
index 5879d71afdaa..c55e43e4d2a4 100644
--- a/include/asm-sparc64/kprobes.h
+++ b/include/asm-sparc64/kprobes.h
@@ -1,49 +1 @@
1#ifndef _SPARC64_KPROBES_H #include <asm-sparc/kprobes.h>
2#define _SPARC64_KPROBES_H
3
4#include <linux/types.h>
5#include <linux/percpu.h>
6
7typedef u32 kprobe_opcode_t;
8
9#define BREAKPOINT_INSTRUCTION 0x91d02070 /* ta 0x70 */
10#define BREAKPOINT_INSTRUCTION_2 0x91d02071 /* ta 0x71 */
11#define MAX_INSN_SIZE 2
12
13#define kretprobe_blacklist_size 0
14
15#define arch_remove_kprobe(p) do {} while (0)
16
17#define flush_insn_slot(p) \
18do { flushi(&(p)->ainsn.insn[0]); \
19 flushi(&(p)->ainsn.insn[1]); \
20} while (0)
21
22void kretprobe_trampoline(void);
23
24/* Architecture specific copy of original instruction*/
25struct arch_specific_insn {
26 /* copy of the original instruction */
27 kprobe_opcode_t insn[MAX_INSN_SIZE];
28};
29
30struct prev_kprobe {
31 struct kprobe *kp;
32 unsigned long status;
33 unsigned long orig_tnpc;
34 unsigned long orig_tstate_pil;
35};
36
37/* per-cpu kprobe control block */
38struct kprobe_ctlblk {
39 unsigned long kprobe_status;
40 unsigned long kprobe_orig_tnpc;
41 unsigned long kprobe_orig_tstate_pil;
42 struct pt_regs jprobe_saved_regs;
43 struct prev_kprobe prev_kprobe;
44};
45
46extern int kprobe_exceptions_notify(struct notifier_block *self,
47 unsigned long val, void *data);
48extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
49#endif /* _SPARC64_KPROBES_H */
diff --git a/include/asm-sparc64/ldc.h b/include/asm-sparc64/ldc.h
index bdb524a7b814..40f3f231c457 100644
--- a/include/asm-sparc64/ldc.h
+++ b/include/asm-sparc64/ldc.h
@@ -1,138 +1 @@
1#ifndef _SPARC64_LDC_H #include <asm-sparc/ldc.h>
2#define _SPARC64_LDC_H
3
4#include <asm/hypervisor.h>
5
6extern int ldom_domaining_enabled;
7extern void ldom_set_var(const char *var, const char *value);
8extern void ldom_reboot(const char *boot_command);
9extern void ldom_power_off(void);
10
11/* The event handler will be evoked when link state changes
12 * or data becomes available on the receive side.
13 *
14 * For non-RAW links, if the LDC_EVENT_RESET event arrives the
15 * driver should reset all of it's internal state and reinvoke
16 * ldc_connect() to try and bring the link up again.
17 *
18 * For RAW links, ldc_connect() is not used. Instead the driver
19 * just waits for the LDC_EVENT_UP event.
20 */
21struct ldc_channel_config {
22 void (*event)(void *arg, int event);
23
24 u32 mtu;
25 unsigned int rx_irq;
26 unsigned int tx_irq;
27 u8 mode;
28#define LDC_MODE_RAW 0x00
29#define LDC_MODE_UNRELIABLE 0x01
30#define LDC_MODE_RESERVED 0x02
31#define LDC_MODE_STREAM 0x03
32
33 u8 debug;
34#define LDC_DEBUG_HS 0x01
35#define LDC_DEBUG_STATE 0x02
36#define LDC_DEBUG_RX 0x04
37#define LDC_DEBUG_TX 0x08
38#define LDC_DEBUG_DATA 0x10
39};
40
41#define LDC_EVENT_RESET 0x01
42#define LDC_EVENT_UP 0x02
43#define LDC_EVENT_DATA_READY 0x04
44
45#define LDC_STATE_INVALID 0x00
46#define LDC_STATE_INIT 0x01
47#define LDC_STATE_BOUND 0x02
48#define LDC_STATE_READY 0x03
49#define LDC_STATE_CONNECTED 0x04
50
51struct ldc_channel;
52
53/* Allocate state for a channel. */
54extern struct ldc_channel *ldc_alloc(unsigned long id,
55 const struct ldc_channel_config *cfgp,
56 void *event_arg);
57
58/* Shut down and free state for a channel. */
59extern void ldc_free(struct ldc_channel *lp);
60
61/* Register TX and RX queues of the link with the hypervisor. */
62extern int ldc_bind(struct ldc_channel *lp, const char *name);
63
64/* For non-RAW protocols we need to complete a handshake before
65 * communication can proceed. ldc_connect() does that, if the
66 * handshake completes successfully, an LDC_EVENT_UP event will
67 * be sent up to the driver.
68 */
69extern int ldc_connect(struct ldc_channel *lp);
70extern int ldc_disconnect(struct ldc_channel *lp);
71
72extern int ldc_state(struct ldc_channel *lp);
73
74/* Read and write operations. Only valid when the link is up. */
75extern int ldc_write(struct ldc_channel *lp, const void *buf,
76 unsigned int size);
77extern int ldc_read(struct ldc_channel *lp, void *buf, unsigned int size);
78
79#define LDC_MAP_SHADOW 0x01
80#define LDC_MAP_DIRECT 0x02
81#define LDC_MAP_IO 0x04
82#define LDC_MAP_R 0x08
83#define LDC_MAP_W 0x10
84#define LDC_MAP_X 0x20
85#define LDC_MAP_RW (LDC_MAP_R | LDC_MAP_W)
86#define LDC_MAP_RWX (LDC_MAP_R | LDC_MAP_W | LDC_MAP_X)
87#define LDC_MAP_ALL 0x03f
88
89struct ldc_trans_cookie {
90 u64 cookie_addr;
91 u64 cookie_size;
92};
93
94struct scatterlist;
95extern int ldc_map_sg(struct ldc_channel *lp,
96 struct scatterlist *sg, int num_sg,
97 struct ldc_trans_cookie *cookies, int ncookies,
98 unsigned int map_perm);
99
100extern int ldc_map_single(struct ldc_channel *lp,
101 void *buf, unsigned int len,
102 struct ldc_trans_cookie *cookies, int ncookies,
103 unsigned int map_perm);
104
105extern void ldc_unmap(struct ldc_channel *lp, struct ldc_trans_cookie *cookies,
106 int ncookies);
107
108extern int ldc_copy(struct ldc_channel *lp, int copy_dir,
109 void *buf, unsigned int len, unsigned long offset,
110 struct ldc_trans_cookie *cookies, int ncookies);
111
112static inline int ldc_get_dring_entry(struct ldc_channel *lp,
113 void *buf, unsigned int len,
114 unsigned long offset,
115 struct ldc_trans_cookie *cookies,
116 int ncookies)
117{
118 return ldc_copy(lp, LDC_COPY_IN, buf, len, offset, cookies, ncookies);
119}
120
121static inline int ldc_put_dring_entry(struct ldc_channel *lp,
122 void *buf, unsigned int len,
123 unsigned long offset,
124 struct ldc_trans_cookie *cookies,
125 int ncookies)
126{
127 return ldc_copy(lp, LDC_COPY_OUT, buf, len, offset, cookies, ncookies);
128}
129
130extern void *ldc_alloc_exp_dring(struct ldc_channel *lp, unsigned int len,
131 struct ldc_trans_cookie *cookies,
132 int *ncookies, unsigned int map_perm);
133
134extern void ldc_free_exp_dring(struct ldc_channel *lp, void *buf,
135 unsigned int len,
136 struct ldc_trans_cookie *cookies, int ncookies);
137
138#endif /* _SPARC64_LDC_H */
diff --git a/include/asm-sparc64/lmb.h b/include/asm-sparc64/lmb.h
index 6a352cbcf520..3d04981701e2 100644
--- a/include/asm-sparc64/lmb.h
+++ b/include/asm-sparc64/lmb.h
@@ -1,10 +1 @@
1#ifndef _SPARC64_LMB_H #include <asm-sparc/lmb.h>
2#define _SPARC64_LMB_H
3
4#include <asm/oplib.h>
5
6#define LMB_DBG(fmt...) prom_printf(fmt)
7
8#define LMB_REAL_LIMIT 0
9
10#endif /* !(_SPARC64_LMB_H) */
diff --git a/include/asm-sparc64/lsu.h b/include/asm-sparc64/lsu.h
index 7190f8de90a0..4e3d8b128a58 100644
--- a/include/asm-sparc64/lsu.h
+++ b/include/asm-sparc64/lsu.h
@@ -1,19 +1 @@
1#ifndef _SPARC64_LSU_H #include <asm-sparc/lsu.h>
2#define _SPARC64_LSU_H
3
4#include <linux/const.h>
5
6/* LSU Control Register */
7#define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
8#define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
9#define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
10#define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
11#define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
12#define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
13#define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
14#define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
15#define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
16#define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
17#define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
18
19#endif /* !(_SPARC64_LSU_H) */
diff --git a/include/asm-sparc64/mdesc.h b/include/asm-sparc64/mdesc.h
index 1acc7272e537..165a19347286 100644
--- a/include/asm-sparc64/mdesc.h
+++ b/include/asm-sparc64/mdesc.h
@@ -1,78 +1 @@
1#ifndef _SPARC64_MDESC_H #include <asm-sparc/mdesc.h>
2#define _SPARC64_MDESC_H
3
4#include <linux/types.h>
5#include <linux/cpumask.h>
6#include <asm/prom.h>
7
8struct mdesc_handle;
9
10/* Machine description operations are to be surrounded by grab and
11 * release calls. The mdesc_handle returned from the grab is
12 * the first argument to all of the operational calls that work
13 * on mdescs.
14 */
15extern struct mdesc_handle *mdesc_grab(void);
16extern void mdesc_release(struct mdesc_handle *);
17
18#define MDESC_NODE_NULL (~(u64)0)
19
20extern u64 mdesc_node_by_name(struct mdesc_handle *handle,
21 u64 from_node, const char *name);
22#define mdesc_for_each_node_by_name(__hdl, __node, __name) \
23 for (__node = mdesc_node_by_name(__hdl, MDESC_NODE_NULL, __name); \
24 (__node) != MDESC_NODE_NULL; \
25 __node = mdesc_node_by_name(__hdl, __node, __name))
26
27/* Access to property values returned from mdesc_get_property() are
28 * only valid inside of a mdesc_grab()/mdesc_release() sequence.
29 * Once mdesc_release() is called, the memory backed up by these
30 * pointers may reference freed up memory.
31 *
32 * Therefore callers must make copies of any property values
33 * they need.
34 *
35 * These same rules apply to mdesc_node_name().
36 */
37extern const void *mdesc_get_property(struct mdesc_handle *handle,
38 u64 node, const char *name, int *lenp);
39extern const char *mdesc_node_name(struct mdesc_handle *hp, u64 node);
40
41/* MD arc iteration, the standard sequence is:
42 *
43 * unsigned long arc;
44 * mdesc_for_each_arc(arc, handle, node, MDESC_ARC_TYPE_{FWD,BACK}) {
45 * unsigned long target = mdesc_arc_target(handle, arc);
46 * ...
47 * }
48 */
49
50#define MDESC_ARC_TYPE_FWD "fwd"
51#define MDESC_ARC_TYPE_BACK "back"
52
53extern u64 mdesc_next_arc(struct mdesc_handle *handle, u64 from,
54 const char *arc_type);
55#define mdesc_for_each_arc(__arc, __hdl, __node, __type) \
56 for (__arc = mdesc_next_arc(__hdl, __node, __type); \
57 (__arc) != MDESC_NODE_NULL; \
58 __arc = mdesc_next_arc(__hdl, __arc, __type))
59
60extern u64 mdesc_arc_target(struct mdesc_handle *hp, u64 arc);
61
62extern void mdesc_update(void);
63
64struct mdesc_notifier_client {
65 void (*add)(struct mdesc_handle *handle, u64 node);
66 void (*remove)(struct mdesc_handle *handle, u64 node);
67
68 const char *node_name;
69 struct mdesc_notifier_client *next;
70};
71
72extern void mdesc_register_notifier(struct mdesc_notifier_client *client);
73
74extern void mdesc_fill_in_cpu_data(cpumask_t mask);
75
76extern void sun4v_mdesc_init(void);
77
78#endif
diff --git a/include/asm-sparc64/mmzone.h b/include/asm-sparc64/mmzone.h
index ebf5986c12ed..43a710f7892a 100644
--- a/include/asm-sparc64/mmzone.h
+++ b/include/asm-sparc64/mmzone.h
@@ -1,17 +1 @@
1#ifndef _SPARC64_MMZONE_H #include <asm-sparc/mmzone.h>
2#define _SPARC64_MMZONE_H
3
4#ifdef CONFIG_NEED_MULTIPLE_NODES
5
6extern struct pglist_data *node_data[];
7
8#define NODE_DATA(nid) (node_data[nid])
9#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
10#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn)
11
12extern int numa_cpu_lookup_table[];
13extern cpumask_t numa_cpumask_lookup_table[];
14
15#endif /* CONFIG_NEED_MULTIPLE_NODES */
16
17#endif /* _SPARC64_MMZONE_H */
diff --git a/include/asm-sparc64/ns87303.h b/include/asm-sparc64/ns87303.h
index 686defe6aaa0..5f369d4df3db 100644
--- a/include/asm-sparc64/ns87303.h
+++ b/include/asm-sparc64/ns87303.h
@@ -1,118 +1 @@
1/* ns87303.h: Configuration Register Description for the #include <asm-sparc/ns87303.h>
2 * National Semiconductor PC87303 (SuperIO).
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 */
6
7#ifndef _SPARC_NS87303_H
8#define _SPARC_NS87303_H 1
9
10/*
11 * Control Register Index Values
12 */
13#define FER 0x00
14#define FAR 0x01
15#define PTR 0x02
16#define FCR 0x03
17#define PCR 0x04
18#define KRR 0x05
19#define PMC 0x06
20#define TUP 0x07
21#define SID 0x08
22#define ASC 0x09
23#define CS0CF0 0x0a
24#define CS0CF1 0x0b
25#define CS1CF0 0x0c
26#define CS1CF1 0x0d
27
28/* Function Enable Register (FER) bits */
29#define FER_EDM 0x10 /* Encoded Drive and Motor pin information */
30
31/* Function Address Register (FAR) bits */
32#define FAR_LPT_MASK 0x03
33#define FAR_LPTB 0x00
34#define FAR_LPTA 0x01
35#define FAR_LPTC 0x02
36
37/* Power and Test Register (PTR) bits */
38#define PTR_LPTB_IRQ7 0x08
39#define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
40#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controlls direction */
41 /* of the parallel port */
42
43/* Function Control Register (FCR) bits */
44#define FCR_LDE 0x10 /* Logical Drive Exchange */
45#define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
46
47/* Printer Control Register (PCR) bits */
48#define PCR_EPP_ENABLE 0x01
49#define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
50#define PCR_ECP_ENABLE 0x04
51#define PCR_ECP_CLK_ENA 0x08 /* If 0 ECP Clock is stopped on Power down */
52#define PCR_IRQ_POLAR 0x20 /* If 0 IRQ is level high or negative pulse, */
53 /* if 1 polarity is inverted */
54#define PCR_IRQ_ODRAIN 0x40 /* If 1, IRQ is open drain */
55
56/* Tape UARTs and Parallel Port Config Register (TUP) bits */
57#define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
58
59/* Advanced SuperIO Config Register (ASC) bits */
60#define ASC_LPT_IRQ7 0x01 /* Always use IRQ7 for LPT */
61#define ASC_DRV2_SEL 0x02 /* Logical Drive Exchange controlled by TDR */
62
63#define FER_RESERVED 0x00
64#define FAR_RESERVED 0x00
65#define PTR_RESERVED 0x73
66#define FCR_RESERVED 0xc4
67#define PCR_RESERVED 0x10
68#define KRR_RESERVED 0x00
69#define PMC_RESERVED 0x98
70#define TUP_RESERVED 0xfb
71#define SIP_RESERVED 0x00
72#define ASC_RESERVED 0x18
73#define CS0CF0_RESERVED 0x00
74#define CS0CF1_RESERVED 0x08
75#define CS1CF0_RESERVED 0x00
76#define CS1CF1_RESERVED 0x08
77
78#ifdef __KERNEL__
79
80#include <linux/spinlock.h>
81
82#include <asm/system.h>
83#include <asm/io.h>
84
85extern spinlock_t ns87303_lock;
86
87static inline int ns87303_modify(unsigned long port, unsigned int index,
88 unsigned char clr, unsigned char set)
89{
90 static unsigned char reserved[] = {
91 FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
92 PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
93 SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
94 CS1CF0_RESERVED, CS1CF1_RESERVED
95 };
96 unsigned long flags;
97 unsigned char value;
98
99 if (index > 0x0d)
100 return -EINVAL;
101
102 spin_lock_irqsave(&ns87303_lock, flags);
103
104 outb(index, port);
105 value = inb(port + 1);
106 value &= ~(reserved[index] | clr);
107 value |= set;
108 outb(value, port + 1);
109 outb(value, port + 1);
110
111 spin_unlock_irqrestore(&ns87303_lock, flags);
112
113 return 0;
114}
115
116#endif /* __KERNEL__ */
117
118#endif /* !(_SPARC_NS87303_H) */
diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h
index e9555b246c8d..b4e4ca812eb6 100644
--- a/include/asm-sparc64/parport.h
+++ b/include/asm-sparc64/parport.h
@@ -1,246 +1 @@
1/* parport.h: sparc64 specific parport initialization and dma. #include <asm-sparc/parport.h>
2 *
3 * Copyright (C) 1999 Eddie C. Dost (ecd@skynet.be)
4 */
5
6#ifndef _ASM_SPARC64_PARPORT_H
7#define _ASM_SPARC64_PARPORT_H 1
8
9#include <asm/ebus.h>
10#include <asm/ns87303.h>
11#include <asm/of_device.h>
12#include <asm/prom.h>
13
14#define PARPORT_PC_MAX_PORTS PARPORT_MAX
15
16/*
17 * While sparc64 doesn't have an ISA DMA API, we provide something that looks
18 * close enough to make parport_pc happy
19 */
20#define HAS_DMA
21
22static DEFINE_SPINLOCK(dma_spin_lock);
23
24#define claim_dma_lock() \
25({ unsigned long flags; \
26 spin_lock_irqsave(&dma_spin_lock, flags); \
27 flags; \
28})
29
30#define release_dma_lock(__flags) \
31 spin_unlock_irqrestore(&dma_spin_lock, __flags);
32
33static struct sparc_ebus_info {
34 struct ebus_dma_info info;
35 unsigned int addr;
36 unsigned int count;
37 int lock;
38
39 struct parport *port;
40} sparc_ebus_dmas[PARPORT_PC_MAX_PORTS];
41
42static DECLARE_BITMAP(dma_slot_map, PARPORT_PC_MAX_PORTS);
43
44static inline int request_dma(unsigned int dmanr, const char *device_id)
45{
46 if (dmanr >= PARPORT_PC_MAX_PORTS)
47 return -EINVAL;
48 if (xchg(&sparc_ebus_dmas[dmanr].lock, 1) != 0)
49 return -EBUSY;
50 return 0;
51}
52
53static inline void free_dma(unsigned int dmanr)
54{
55 if (dmanr >= PARPORT_PC_MAX_PORTS) {
56 printk(KERN_WARNING "Trying to free DMA%d\n", dmanr);
57 return;
58 }
59 if (xchg(&sparc_ebus_dmas[dmanr].lock, 0) == 0) {
60 printk(KERN_WARNING "Trying to free free DMA%d\n", dmanr);
61 return;
62 }
63}
64
65static inline void enable_dma(unsigned int dmanr)
66{
67 ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
68
69 if (ebus_dma_request(&sparc_ebus_dmas[dmanr].info,
70 sparc_ebus_dmas[dmanr].addr,
71 sparc_ebus_dmas[dmanr].count))
72 BUG();
73}
74
75static inline void disable_dma(unsigned int dmanr)
76{
77 ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 0);
78}
79
80static inline void clear_dma_ff(unsigned int dmanr)
81{
82 /* nothing */
83}
84
85static inline void set_dma_mode(unsigned int dmanr, char mode)
86{
87 ebus_dma_prepare(&sparc_ebus_dmas[dmanr].info, (mode != DMA_MODE_WRITE));
88}
89
90static inline void set_dma_addr(unsigned int dmanr, unsigned int addr)
91{
92 sparc_ebus_dmas[dmanr].addr = addr;
93}
94
95static inline void set_dma_count(unsigned int dmanr, unsigned int count)
96{
97 sparc_ebus_dmas[dmanr].count = count;
98}
99
100static inline unsigned int get_dma_residue(unsigned int dmanr)
101{
102 return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info);
103}
104
105static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id *match)
106{
107 unsigned long base = op->resource[0].start;
108 unsigned long config = op->resource[1].start;
109 unsigned long d_base = op->resource[2].start;
110 unsigned long d_len;
111 struct device_node *parent;
112 struct parport *p;
113 int slot, err;
114
115 parent = op->node->parent;
116 if (!strcmp(parent->name, "dma")) {
117 p = parport_pc_probe_port(base, base + 0x400,
118 op->irqs[0], PARPORT_DMA_NOFIFO,
119 op->dev.parent->parent);
120 if (!p)
121 return -ENOMEM;
122 dev_set_drvdata(&op->dev, p);
123 return 0;
124 }
125
126 for (slot = 0; slot < PARPORT_PC_MAX_PORTS; slot++) {
127 if (!test_and_set_bit(slot, dma_slot_map))
128 break;
129 }
130 err = -ENODEV;
131 if (slot >= PARPORT_PC_MAX_PORTS)
132 goto out_err;
133
134 spin_lock_init(&sparc_ebus_dmas[slot].info.lock);
135
136 d_len = (op->resource[2].end - d_base) + 1UL;
137 sparc_ebus_dmas[slot].info.regs =
138 of_ioremap(&op->resource[2], 0, d_len, "ECPP DMA");
139
140 if (!sparc_ebus_dmas[slot].info.regs)
141 goto out_clear_map;
142
143 sparc_ebus_dmas[slot].info.flags = 0;
144 sparc_ebus_dmas[slot].info.callback = NULL;
145 sparc_ebus_dmas[slot].info.client_cookie = NULL;
146 sparc_ebus_dmas[slot].info.irq = 0xdeadbeef;
147 strcpy(sparc_ebus_dmas[slot].info.name, "parport");
148 if (ebus_dma_register(&sparc_ebus_dmas[slot].info))
149 goto out_unmap_regs;
150
151 ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 1);
152
153 /* Configure IRQ to Push Pull, Level Low */
154 /* Enable ECP, set bit 2 of the CTR first */
155 outb(0x04, base + 0x02);
156 ns87303_modify(config, PCR,
157 PCR_EPP_ENABLE |
158 PCR_IRQ_ODRAIN,
159 PCR_ECP_ENABLE |
160 PCR_ECP_CLK_ENA |
161 PCR_IRQ_POLAR);
162
163 /* CTR bit 5 controls direction of port */
164 ns87303_modify(config, PTR,
165 0, PTR_LPT_REG_DIR);
166
167 p = parport_pc_probe_port(base, base + 0x400,
168 op->irqs[0],
169 slot,
170 op->dev.parent);
171 err = -ENOMEM;
172 if (!p)
173 goto out_disable_irq;
174
175 dev_set_drvdata(&op->dev, p);
176
177 return 0;
178
179out_disable_irq:
180 ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
181 ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
182
183out_unmap_regs:
184 of_iounmap(&op->resource[2], sparc_ebus_dmas[slot].info.regs, d_len);
185
186out_clear_map:
187 clear_bit(slot, dma_slot_map);
188
189out_err:
190 return err;
191}
192
193static int __devexit ecpp_remove(struct of_device *op)
194{
195 struct parport *p = dev_get_drvdata(&op->dev);
196 int slot = p->dma;
197
198 parport_pc_unregister_port(p);
199
200 if (slot != PARPORT_DMA_NOFIFO) {
201 unsigned long d_base = op->resource[2].start;
202 unsigned long d_len;
203
204 d_len = (op->resource[2].end - d_base) + 1UL;
205
206 ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
207 ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
208 of_iounmap(&op->resource[2],
209 sparc_ebus_dmas[slot].info.regs,
210 d_len);
211 clear_bit(slot, dma_slot_map);
212 }
213
214 return 0;
215}
216
217static struct of_device_id ecpp_match[] = {
218 {
219 .name = "ecpp",
220 },
221 {
222 .name = "parallel",
223 .compatible = "ecpp",
224 },
225 {
226 .name = "parallel",
227 .compatible = "ns87317-ecpp",
228 },
229 {},
230};
231
232static struct of_platform_driver ecpp_driver = {
233 .name = "ecpp",
234 .match_table = ecpp_match,
235 .probe = ecpp_probe,
236 .remove = __devexit_p(ecpp_remove),
237};
238
239static int parport_pc_find_nonpci_ports(int autoirq, int autodma)
240{
241 of_register_driver(&ecpp_driver, &of_bus_type);
242
243 return 0;
244}
245
246#endif /* !(_ASM_SPARC64_PARPORT_H */
diff --git a/include/asm-sparc64/pil.h b/include/asm-sparc64/pil.h
index eaac842d88c3..d805f33f1e0f 100644
--- a/include/asm-sparc64/pil.h
+++ b/include/asm-sparc64/pil.h
@@ -1,21 +1 @@
1#ifndef _SPARC64_PIL_H #include <asm-sparc/pil.h>
2#define _SPARC64_PIL_H
3
4/* To avoid some locking problems, we hard allocate certain PILs
5 * for SMP cross call messages that must do a etrap/rtrap.
6 *
7 * A local_irq_disable() does not block the cross call delivery, so
8 * when SMP locking is an issue we reschedule the event into a PIL
9 * interrupt which is blocked by local_irq_disable().
10 *
11 * In fact any XCALL which has to etrap/rtrap has a problem because
12 * it is difficult to prevent rtrap from running BH's, and that would
13 * need to be done if the XCALL arrived while %pil==15.
14 */
15#define PIL_SMP_CALL_FUNC 1
16#define PIL_SMP_RECEIVE_SIGNAL 2
17#define PIL_SMP_CAPTURE 3
18#define PIL_SMP_CTX_NEW_VERSION 4
19#define PIL_DEVICE_IRQ 5
20
21#endif /* !(_SPARC64_PIL_H) */
diff --git a/include/asm-sparc64/reboot.h b/include/asm-sparc64/reboot.h
index 3f3f43f5be5e..0d72eb811cc8 100644
--- a/include/asm-sparc64/reboot.h
+++ b/include/asm-sparc64/reboot.h
@@ -1,6 +1 @@
1#ifndef _SPARC64_REBOOT_H #include <asm-sparc/reboot.h>
2#define _SPARC64_REBOOT_H
3
4extern void machine_alt_power_off(void);
5
6#endif /* _SPARC64_REBOOT_H */
diff --git a/include/asm-sparc64/rwsem-const.h b/include/asm-sparc64/rwsem-const.h
index a303c9d64d84..2a1de315c86a 100644
--- a/include/asm-sparc64/rwsem-const.h
+++ b/include/asm-sparc64/rwsem-const.h
@@ -1,12 +1 @@
1/* rwsem-const.h: RW semaphore counter constants. */ #include <asm-sparc/rwsem-const.h>
2#ifndef _SPARC64_RWSEM_CONST_H
3#define _SPARC64_RWSEM_CONST_H
4
5#define RWSEM_UNLOCKED_VALUE 0x00000000
6#define RWSEM_ACTIVE_BIAS 0x00000001
7#define RWSEM_ACTIVE_MASK 0x0000ffff
8#define RWSEM_WAITING_BIAS 0xffff0000
9#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
10#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
11
12#endif /* _SPARC64_RWSEM_CONST_H */
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index 1dc129ac2feb..6943c56ed087 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -1,84 +1 @@
1/* #include <asm-sparc/rwsem.h>
2 * rwsem.h: R/W semaphores implemented using CAS
3 *
4 * Written by David S. Miller (davem@redhat.com), 2001.
5 * Derived from asm-i386/rwsem.h
6 */
7#ifndef _SPARC64_RWSEM_H
8#define _SPARC64_RWSEM_H
9
10#ifndef _LINUX_RWSEM_H
11#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
12#endif
13
14#ifdef __KERNEL__
15
16#include <linux/list.h>
17#include <linux/spinlock.h>
18#include <asm/rwsem-const.h>
19
20struct rwsem_waiter;
21
22struct rw_semaphore {
23 signed int count;
24 spinlock_t wait_lock;
25 struct list_head wait_list;
26#ifdef CONFIG_DEBUG_LOCK_ALLOC
27 struct lockdep_map dep_map;
28#endif
29};
30
31#ifdef CONFIG_DEBUG_LOCK_ALLOC
32# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
33#else
34# define __RWSEM_DEP_MAP_INIT(lockname)
35#endif
36
37#define __RWSEM_INITIALIZER(name) \
38{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
39 __RWSEM_DEP_MAP_INIT(name) }
40
41#define DECLARE_RWSEM(name) \
42 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
43
44extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
45 struct lock_class_key *key);
46
47#define init_rwsem(sem) \
48do { \
49 static struct lock_class_key __key; \
50 \
51 __init_rwsem((sem), #sem, &__key); \
52} while (0)
53
54extern void __down_read(struct rw_semaphore *sem);
55extern int __down_read_trylock(struct rw_semaphore *sem);
56extern void __down_write(struct rw_semaphore *sem);
57extern int __down_write_trylock(struct rw_semaphore *sem);
58extern void __up_read(struct rw_semaphore *sem);
59extern void __up_write(struct rw_semaphore *sem);
60extern void __downgrade_write(struct rw_semaphore *sem);
61
62static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
63{
64 __down_write(sem);
65}
66
67static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
68{
69 return atomic_add_return(delta, (atomic_t *)(&sem->count));
70}
71
72static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
73{
74 atomic_add(delta, (atomic_t *)(&sem->count));
75}
76
77static inline int rwsem_is_locked(struct rw_semaphore *sem)
78{
79 return (sem->count != 0);
80}
81
82#endif /* __KERNEL__ */
83
84#endif /* _SPARC64_RWSEM_H */
diff --git a/include/asm-sparc64/scratchpad.h b/include/asm-sparc64/scratchpad.h
index 5e8b01fb3343..23675f6a915a 100644
--- a/include/asm-sparc64/scratchpad.h
+++ b/include/asm-sparc64/scratchpad.h
@@ -1,14 +1 @@
1#ifndef _SPARC64_SCRATCHPAD_H #include <asm-sparc/scratchpad.h>
2#define _SPARC64_SCRATCHPAD_H
3
4/* Sun4v scratchpad registers, accessed via ASI_SCRATCHPAD. */
5
6#define SCRATCHPAD_MMU_MISS 0x00 /* Shared with OBP - set by OBP */
7#define SCRATCHPAD_CPUID 0x08 /* Shared with OBP - set by hypervisor */
8#define SCRATCHPAD_UTSBREG1 0x10
9#define SCRATCHPAD_UTSBREG2 0x18
10 /* 0x20 and 0x28, hypervisor only... */
11#define SCRATCHPAD_UNUSED1 0x30
12#define SCRATCHPAD_UNUSED2 0x38 /* Reserved for OBP */
13
14#endif /* !(_SPARC64_SCRATCHPAD_H) */
diff --git a/include/asm-sparc64/seccomp.h b/include/asm-sparc64/seccomp.h
index 7fcd9968192b..f22f02a08a61 100644
--- a/include/asm-sparc64/seccomp.h
+++ b/include/asm-sparc64/seccomp.h
@@ -1,21 +1 @@
1#ifndef _ASM_SECCOMP_H #include <asm-sparc/seccomp.h>
2
3#include <linux/thread_info.h> /* already defines TIF_32BIT */
4
5#ifndef TIF_32BIT
6#error "unexpected TIF_32BIT on sparc64"
7#endif
8
9#include <linux/unistd.h>
10
11#define __NR_seccomp_read __NR_read
12#define __NR_seccomp_write __NR_write
13#define __NR_seccomp_exit __NR_exit
14#define __NR_seccomp_sigreturn __NR_rt_sigreturn
15
16#define __NR_seccomp_read_32 __NR_read
17#define __NR_seccomp_write_32 __NR_write
18#define __NR_seccomp_exit_32 __NR_exit
19#define __NR_seccomp_sigreturn_32 __NR_sigreturn
20
21#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-sparc64/sfafsr.h b/include/asm-sparc64/sfafsr.h
index e96137b04a4f..8036fc377a4d 100644
--- a/include/asm-sparc64/sfafsr.h
+++ b/include/asm-sparc64/sfafsr.h
@@ -1,82 +1 @@
1#ifndef _SPARC64_SFAFSR_H #include <asm-sparc/sfafsr.h>
2#define _SPARC64_SFAFSR_H
3
4#include <linux/const.h>
5
6/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
7
8#define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
9#define SFAFSR_ME_SHIFT 32
10#define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
11#define SFAFSR_PRIV_SHIFT 31
12#define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
13#define SFAFSR_ISAP_SHIFT 30
14#define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
15#define SFAFSR_ETP_SHIFT 29
16#define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
17#define SFAFSR_IVUE_SHIFT 28
18#define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
19#define SFAFSR_TO_SHIFT 27
20#define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
21#define SFAFSR_BERR_SHIFT 26
22#define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
23#define SFAFSR_LDP_SHIFT 25
24#define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
25#define SFAFSR_CP_SHIFT 24
26#define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
27#define SFAFSR_WP_SHIFT 23
28#define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT)
29#define SFAFSR_EDP_SHIFT 22
30#define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT)
31#define SFAFSR_UE_SHIFT 21
32#define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT)
33#define SFAFSR_CE_SHIFT 20
34#define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
35#define SFAFSR_ETS_SHIFT 16
36#define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
37#define SFAFSR_PSYND_SHIFT 0
38
39/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read
40 * ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write
41 */
42
43#define UDBE_UE (_AC(1,UL) << 9)
44#define UDBE_CE (_AC(1,UL) << 8)
45#define UDBE_E_SYNDR (_AC(0xff,UL) << 0)
46
47/* The trap handlers for asynchronous errors encode the AFSR and
48 * other pieces of information into a 64-bit argument for C code
49 * encoded as follows:
50 *
51 * -----------------------------------------------
52 * | UDB_H | UDB_L | TL>1 | TT | AFSR |
53 * -----------------------------------------------
54 * 63 54 53 44 42 41 33 32 0
55 *
56 * The AFAR is passed in unchanged.
57 */
58#define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
59#define SFSTAT_UDBH_SHIFT 54
60#define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
61#define SFSTAT_UDBL_SHIFT 44
62#define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
63#define SFSTAT_TL_GT_ONE_SHIFT 42
64#define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
65#define SFSTAT_TRAP_TYPE_SHIFT 33
66#define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
67#define SFSTAT_AFSR_SHIFT 0
68
69/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */
70#define ESTATE_ERR_CE 0x1 /* Correctable errors */
71#define ESTATE_ERR_NCE 0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */
72#define ESTATE_ERR_ISAP 0x4 /* System address parity error */
73#define ESTATE_ERR_ALL (ESTATE_ERR_CE | \
74 ESTATE_ERR_NCE | \
75 ESTATE_ERR_ISAP)
76
77/* The various trap types that report using the above state. */
78#define TRAP_TYPE_IAE 0x09 /* Instruction Access Error */
79#define TRAP_TYPE_DAE 0x32 /* Data Access Error */
80#define TRAP_TYPE_CEE 0x63 /* Correctable ECC Error */
81
82#endif /* _SPARC64_SFAFSR_H */
diff --git a/include/asm-sparc64/sparsemem.h b/include/asm-sparc64/sparsemem.h
index b99d4e4b6d28..e681f22a97ae 100644
--- a/include/asm-sparc64/sparsemem.h
+++ b/include/asm-sparc64/sparsemem.h
@@ -1,12 +1 @@
1#ifndef _SPARC64_SPARSEMEM_H #include <asm-sparc/sparsemem.h>
2#define _SPARC64_SPARSEMEM_H
3
4#ifdef __KERNEL__
5
6#define SECTION_SIZE_BITS 30
7#define MAX_PHYSADDR_BITS 42
8#define MAX_PHYSMEM_BITS 42
9
10#endif /* !(__KERNEL__) */
11
12#endif /* !(_SPARC64_SPARSEMEM_H) */
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index 985ea7e31992..4430d2fbb0dc 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -1,342 +1 @@
1/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations. #include <asm-sparc/spitfire.h>
2 *
3 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_SPITFIRE_H
7#define _SPARC64_SPITFIRE_H
8
9#include <asm/asi.h>
10
11/* The following register addresses are accessible via ASI_DMMU
12 * and ASI_IMMU, that is there is a distinct and unique copy of
13 * each these registers for each TLB.
14 */
15#define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
16#define TLB_SFSR 0x0000000000000018 /* All chips */
17#define TSB_REG 0x0000000000000028 /* All chips */
18#define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
19#define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
20#define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
21#define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
22#define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
23#define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
24#define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
25
26/* These registers only exist as one entity, and are accessed
27 * via ASI_DMMU only.
28 */
29#define PRIMARY_CONTEXT 0x0000000000000008
30#define SECONDARY_CONTEXT 0x0000000000000010
31#define DMMU_SFAR 0x0000000000000020
32#define VIRT_WATCHPOINT 0x0000000000000038
33#define PHYS_WATCHPOINT 0x0000000000000040
34
35#define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
36#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
37
38#define L1DCACHE_SIZE 0x4000
39
40#define SUN4V_CHIP_INVALID 0x00
41#define SUN4V_CHIP_NIAGARA1 0x01
42#define SUN4V_CHIP_NIAGARA2 0x02
43#define SUN4V_CHIP_UNKNOWN 0xff
44
45#ifndef __ASSEMBLY__
46
47enum ultra_tlb_layout {
48 spitfire = 0,
49 cheetah = 1,
50 cheetah_plus = 2,
51 hypervisor = 3,
52};
53
54extern enum ultra_tlb_layout tlb_type;
55
56extern int sun4v_chip_type;
57
58extern int cheetah_pcache_forced_on;
59extern void cheetah_enable_pcache(void);
60
61#define sparc64_highest_locked_tlbent() \
62 (tlb_type == spitfire ? \
63 SPITFIRE_HIGHEST_LOCKED_TLBENT : \
64 CHEETAH_HIGHEST_LOCKED_TLBENT)
65
66extern int num_kernel_image_mappings;
67
68/* The data cache is write through, so this just invalidates the
69 * specified line.
70 */
71static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
72{
73 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
74 "membar #Sync"
75 : /* No outputs */
76 : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
77}
78
79/* The instruction cache lines are flushed with this, but note that
80 * this does not flush the pipeline. It is possible for a line to
81 * get flushed but stale instructions to still be in the pipeline,
82 * a flush instruction (to any address) is sufficient to handle
83 * this issue after the line is invalidated.
84 */
85static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
86{
87 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
88 "membar #Sync"
89 : /* No outputs */
90 : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
91}
92
93static inline unsigned long spitfire_get_dtlb_data(int entry)
94{
95 unsigned long data;
96
97 __asm__ __volatile__("ldxa [%1] %2, %0"
98 : "=r" (data)
99 : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
100
101 /* Clear TTE diag bits. */
102 data &= ~0x0003fe0000000000UL;
103
104 return data;
105}
106
107static inline unsigned long spitfire_get_dtlb_tag(int entry)
108{
109 unsigned long tag;
110
111 __asm__ __volatile__("ldxa [%1] %2, %0"
112 : "=r" (tag)
113 : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
114 return tag;
115}
116
117static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
118{
119 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
120 "membar #Sync"
121 : /* No outputs */
122 : "r" (data), "r" (entry << 3),
123 "i" (ASI_DTLB_DATA_ACCESS));
124}
125
126static inline unsigned long spitfire_get_itlb_data(int entry)
127{
128 unsigned long data;
129
130 __asm__ __volatile__("ldxa [%1] %2, %0"
131 : "=r" (data)
132 : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
133
134 /* Clear TTE diag bits. */
135 data &= ~0x0003fe0000000000UL;
136
137 return data;
138}
139
140static inline unsigned long spitfire_get_itlb_tag(int entry)
141{
142 unsigned long tag;
143
144 __asm__ __volatile__("ldxa [%1] %2, %0"
145 : "=r" (tag)
146 : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
147 return tag;
148}
149
150static inline void spitfire_put_itlb_data(int entry, unsigned long data)
151{
152 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
153 "membar #Sync"
154 : /* No outputs */
155 : "r" (data), "r" (entry << 3),
156 "i" (ASI_ITLB_DATA_ACCESS));
157}
158
159static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
160{
161 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
162 "membar #Sync"
163 : /* No outputs */
164 : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
165}
166
167static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
168{
169 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
170 "membar #Sync"
171 : /* No outputs */
172 : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
173}
174
175/* Cheetah has "all non-locked" tlb flushes. */
176static inline void cheetah_flush_dtlb_all(void)
177{
178 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
179 "membar #Sync"
180 : /* No outputs */
181 : "r" (0x80), "i" (ASI_DMMU_DEMAP));
182}
183
184static inline void cheetah_flush_itlb_all(void)
185{
186 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
187 "membar #Sync"
188 : /* No outputs */
189 : "r" (0x80), "i" (ASI_IMMU_DEMAP));
190}
191
192/* Cheetah has a 4-tlb layout so direct access is a bit different.
193 * The first two TLBs are fully assosciative, hold 16 entries, and are
194 * used only for locked and >8K sized translations. One exists for
195 * data accesses and one for instruction accesses.
196 *
197 * The third TLB is for data accesses to 8K non-locked translations, is
198 * 2 way assosciative, and holds 512 entries. The fourth TLB is for
199 * instruction accesses to 8K non-locked translations, is 2 way
200 * assosciative, and holds 128 entries.
201 *
202 * Cheetah has some bug where bogus data can be returned from
203 * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
204 * the problem for me. -DaveM
205 */
206static inline unsigned long cheetah_get_ldtlb_data(int entry)
207{
208 unsigned long data;
209
210 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
211 "ldxa [%1] %2, %0"
212 : "=r" (data)
213 : "r" ((0 << 16) | (entry << 3)),
214 "i" (ASI_DTLB_DATA_ACCESS));
215
216 return data;
217}
218
219static inline unsigned long cheetah_get_litlb_data(int entry)
220{
221 unsigned long data;
222
223 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
224 "ldxa [%1] %2, %0"
225 : "=r" (data)
226 : "r" ((0 << 16) | (entry << 3)),
227 "i" (ASI_ITLB_DATA_ACCESS));
228
229 return data;
230}
231
232static inline unsigned long cheetah_get_ldtlb_tag(int entry)
233{
234 unsigned long tag;
235
236 __asm__ __volatile__("ldxa [%1] %2, %0"
237 : "=r" (tag)
238 : "r" ((0 << 16) | (entry << 3)),
239 "i" (ASI_DTLB_TAG_READ));
240
241 return tag;
242}
243
244static inline unsigned long cheetah_get_litlb_tag(int entry)
245{
246 unsigned long tag;
247
248 __asm__ __volatile__("ldxa [%1] %2, %0"
249 : "=r" (tag)
250 : "r" ((0 << 16) | (entry << 3)),
251 "i" (ASI_ITLB_TAG_READ));
252
253 return tag;
254}
255
256static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
257{
258 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
259 "membar #Sync"
260 : /* No outputs */
261 : "r" (data),
262 "r" ((0 << 16) | (entry << 3)),
263 "i" (ASI_DTLB_DATA_ACCESS));
264}
265
266static inline void cheetah_put_litlb_data(int entry, unsigned long data)
267{
268 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
269 "membar #Sync"
270 : /* No outputs */
271 : "r" (data),
272 "r" ((0 << 16) | (entry << 3)),
273 "i" (ASI_ITLB_DATA_ACCESS));
274}
275
276static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
277{
278 unsigned long data;
279
280 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
281 "ldxa [%1] %2, %0"
282 : "=r" (data)
283 : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
284
285 return data;
286}
287
288static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
289{
290 unsigned long tag;
291
292 __asm__ __volatile__("ldxa [%1] %2, %0"
293 : "=r" (tag)
294 : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
295 return tag;
296}
297
298static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
299{
300 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
301 "membar #Sync"
302 : /* No outputs */
303 : "r" (data),
304 "r" ((tlb << 16) | (entry << 3)),
305 "i" (ASI_DTLB_DATA_ACCESS));
306}
307
308static inline unsigned long cheetah_get_itlb_data(int entry)
309{
310 unsigned long data;
311
312 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
313 "ldxa [%1] %2, %0"
314 : "=r" (data)
315 : "r" ((2 << 16) | (entry << 3)),
316 "i" (ASI_ITLB_DATA_ACCESS));
317
318 return data;
319}
320
321static inline unsigned long cheetah_get_itlb_tag(int entry)
322{
323 unsigned long tag;
324
325 __asm__ __volatile__("ldxa [%1] %2, %0"
326 : "=r" (tag)
327 : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
328 return tag;
329}
330
331static inline void cheetah_put_itlb_data(int entry, unsigned long data)
332{
333 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
334 "membar #Sync"
335 : /* No outputs */
336 : "r" (data), "r" ((2 << 16) | (entry << 3)),
337 "i" (ASI_ITLB_DATA_ACCESS));
338}
339
340#endif /* !(__ASSEMBLY__) */
341
342#endif /* !(_SPARC64_SPITFIRE_H) */
diff --git a/include/asm-sparc64/sstate.h b/include/asm-sparc64/sstate.h
index a7c35dbcb281..97720ce2fd43 100644
--- a/include/asm-sparc64/sstate.h
+++ b/include/asm-sparc64/sstate.h
@@ -1,13 +1 @@
1#ifndef _SPARC64_SSTATE_H #include <asm-sparc/sstate.h>
2#define _SPARC64_SSTATE_H
3
4extern void sstate_booting(void);
5extern void sstate_running(void);
6extern void sstate_halt(void);
7extern void sstate_poweroff(void);
8extern void sstate_panic(void);
9extern void sstate_reboot(void);
10
11extern void sun4v_sstate_init(void);
12
13#endif /* _SPARC64_SSTATE_H */
diff --git a/include/asm-sparc64/stacktrace.h b/include/asm-sparc64/stacktrace.h
index 6cee39adf6d6..adc9b92c0ef1 100644
--- a/include/asm-sparc64/stacktrace.h
+++ b/include/asm-sparc64/stacktrace.h
@@ -1,6 +1 @@
1#ifndef _SPARC64_STACKTRACE_H #include <asm-sparc/stacktrace.h>
2#define _SPARC64_STACKTRACE_H
3
4extern void stack_trace_flush(void);
5
6#endif /* _SPARC64_STACKTRACE_H */
diff --git a/include/asm-sparc64/starfire.h b/include/asm-sparc64/starfire.h
index 07bafd31e33c..db97daa3bed4 100644
--- a/include/asm-sparc64/starfire.h
+++ b/include/asm-sparc64/starfire.h
@@ -1,21 +1 @@
1/* #include <asm-sparc/starfire.h>
2 * starfire.h: Group all starfire specific code together.
3 *
4 * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
5 */
6
7#ifndef _SPARC64_STARFIRE_H
8#define _SPARC64_STARFIRE_H
9
10#ifndef __ASSEMBLY__
11
12extern int this_is_starfire;
13
14extern void check_if_starfire(void);
15extern void starfire_cpu_setup(void);
16extern int starfire_hard_smp_processor_id(void);
17extern void starfire_hookup(int);
18extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
19
20#endif
21#endif
diff --git a/include/asm-sparc64/syscalls.h b/include/asm-sparc64/syscalls.h
index 45a43f637a14..3477b16e30ca 100644
--- a/include/asm-sparc64/syscalls.h
+++ b/include/asm-sparc64/syscalls.h
@@ -1,13 +1 @@
1#ifndef _SPARC64_SYSCALLS_H #include <asm-sparc/syscalls.h>
2#define _SPARC64_SYSCALLS_H
3
4struct pt_regs;
5
6extern asmlinkage long sparc_do_fork(unsigned long clone_flags,
7 unsigned long stack_start,
8 struct pt_regs *regs,
9 unsigned long stack_size);
10
11extern asmlinkage int sparc_execve(struct pt_regs *regs);
12
13#endif /* _SPARC64_SYSCALLS_H */
diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h
index 76e4299dd9bc..3677a302ea3e 100644
--- a/include/asm-sparc64/tsb.h
+++ b/include/asm-sparc64/tsb.h
@@ -1,283 +1 @@
1#ifndef _SPARC64_TSB_H #include <asm-sparc/tsb.h>
2#define _SPARC64_TSB_H
3
4/* The sparc64 TSB is similar to the powerpc hashtables. It's a
5 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
6 * pointers into this table for 8K and 64K page sizes, and also a
7 * comparison TAG based upon the virtual address and context which
8 * faults.
9 *
10 * TLB miss trap handler software does the actual lookup via something
11 * of the form:
12 *
13 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
14 * ldxa [%g0] ASI_{D,I}MMU, %g6
15 * sllx %g6, 22, %g6
16 * srlx %g6, 22, %g6
17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
18 * cmp %g4, %g6
19 * bne,pn %xcc, tsb_miss_{d,i}tlb
20 * mov FAULT_CODE_{D,I}TLB, %g3
21 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
22 * retry
23 *
24 *
25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
26 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
27 * register which is:
28 *
29 * -------------------------------------------------
30 * | - | CONTEXT | - | VADDR bits 63:22 |
31 * -------------------------------------------------
32 * 63 61 60 48 47 42 41 0
33 *
34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
35 * field.
36 *
37 * Like the powerpc hashtables we need to use locking in order to
38 * synchronize while we update the entries. PTE updates need locking
39 * as well.
40 *
41 * We need to carefully choose a lock bits for the TSB entry. We
42 * choose to use bit 47 in the tag. Also, since we never map anything
43 * at page zero in context zero, we use zero as an invalid tag entry.
44 * When the lock bit is set, this forces a tag comparison failure.
45 */
46
47#define TSB_TAG_LOCK_BIT 47
48#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
49
50#define TSB_TAG_INVALID_BIT 46
51#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
52
53#define TSB_MEMBAR membar #StoreStore
54
55/* Some cpus support physical address quad loads. We want to use
56 * those if possible so we don't need to hard-lock the TSB mapping
57 * into the TLB. We encode some instruction patching in order to
58 * support this.
59 *
60 * The kernel TSB is locked into the TLB by virtue of being in the
61 * kernel image, so we don't play these games for swapper_tsb access.
62 */
63#ifndef __ASSEMBLY__
64struct tsb_ldquad_phys_patch_entry {
65 unsigned int addr;
66 unsigned int sun4u_insn;
67 unsigned int sun4v_insn;
68};
69extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
70 __tsb_ldquad_phys_patch_end;
71
72struct tsb_phys_patch_entry {
73 unsigned int addr;
74 unsigned int insn;
75};
76extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
77#endif
78#define TSB_LOAD_QUAD(TSB, REG) \
79661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
80 .section .tsb_ldquad_phys_patch, "ax"; \
81 .word 661b; \
82 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
83 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
84 .previous
85
86#define TSB_LOAD_TAG_HIGH(TSB, REG) \
87661: lduwa [TSB] ASI_N, REG; \
88 .section .tsb_phys_patch, "ax"; \
89 .word 661b; \
90 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
91 .previous
92
93#define TSB_LOAD_TAG(TSB, REG) \
94661: ldxa [TSB] ASI_N, REG; \
95 .section .tsb_phys_patch, "ax"; \
96 .word 661b; \
97 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
98 .previous
99
100#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
101661: casa [TSB] ASI_N, REG1, REG2; \
102 .section .tsb_phys_patch, "ax"; \
103 .word 661b; \
104 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 .previous
106
107#define TSB_CAS_TAG(TSB, REG1, REG2) \
108661: casxa [TSB] ASI_N, REG1, REG2; \
109 .section .tsb_phys_patch, "ax"; \
110 .word 661b; \
111 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
112 .previous
113
114#define TSB_STORE(ADDR, VAL) \
115661: stxa VAL, [ADDR] ASI_N; \
116 .section .tsb_phys_patch, "ax"; \
117 .word 661b; \
118 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
119 .previous
120
121#define TSB_LOCK_TAG(TSB, REG1, REG2) \
12299: TSB_LOAD_TAG_HIGH(TSB, REG1); \
123 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
124 andcc REG1, REG2, %g0; \
125 bne,pn %icc, 99b; \
126 nop; \
127 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
128 cmp REG1, REG2; \
129 bne,pn %icc, 99b; \
130 nop; \
131 TSB_MEMBAR
132
133#define TSB_WRITE(TSB, TTE, TAG) \
134 add TSB, 0x8, TSB; \
135 TSB_STORE(TSB, TTE); \
136 sub TSB, 0x8, TSB; \
137 TSB_MEMBAR; \
138 TSB_STORE(TSB, TAG);
139
140#define KTSB_LOAD_QUAD(TSB, REG) \
141 ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
142
143#define KTSB_STORE(ADDR, VAL) \
144 stxa VAL, [ADDR] ASI_N;
145
146#define KTSB_LOCK_TAG(TSB, REG1, REG2) \
14799: lduwa [TSB] ASI_N, REG1; \
148 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
149 andcc REG1, REG2, %g0; \
150 bne,pn %icc, 99b; \
151 nop; \
152 casa [TSB] ASI_N, REG1, REG2;\
153 cmp REG1, REG2; \
154 bne,pn %icc, 99b; \
155 nop; \
156 TSB_MEMBAR
157
158#define KTSB_WRITE(TSB, TTE, TAG) \
159 add TSB, 0x8, TSB; \
160 stxa TTE, [TSB] ASI_N; \
161 sub TSB, 0x8, TSB; \
162 TSB_MEMBAR; \
163 stxa TAG, [TSB] ASI_N;
164
165 /* Do a kernel page table walk. Leaves physical PTE pointer in
166 * REG1. Jumps to FAIL_LABEL on early page table walk termination.
167 * VADDR will not be clobbered, but REG2 will.
168 */
169#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
170 sethi %hi(swapper_pg_dir), REG1; \
171 or REG1, %lo(swapper_pg_dir), REG1; \
172 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
173 srlx REG2, 64 - PAGE_SHIFT, REG2; \
174 andn REG2, 0x3, REG2; \
175 lduw [REG1 + REG2], REG1; \
176 brz,pn REG1, FAIL_LABEL; \
177 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
178 srlx REG2, 64 - PAGE_SHIFT, REG2; \
179 sllx REG1, 11, REG1; \
180 andn REG2, 0x3, REG2; \
181 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
182 brz,pn REG1, FAIL_LABEL; \
183 sllx VADDR, 64 - PMD_SHIFT, REG2; \
184 srlx REG2, 64 - PAGE_SHIFT, REG2; \
185 sllx REG1, 11, REG1; \
186 andn REG2, 0x7, REG2; \
187 add REG1, REG2, REG1;
188
189 /* Do a user page table walk in MMU globals. Leaves physical PTE
190 * pointer in REG1. Jumps to FAIL_LABEL on early page table walk
191 * termination. Physical base of page tables is in PHYS_PGD which
192 * will not be modified.
193 *
194 * VADDR will not be clobbered, but REG1 and REG2 will.
195 */
196#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
197 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
198 srlx REG2, 64 - PAGE_SHIFT, REG2; \
199 andn REG2, 0x3, REG2; \
200 lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
201 brz,pn REG1, FAIL_LABEL; \
202 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
203 srlx REG2, 64 - PAGE_SHIFT, REG2; \
204 sllx REG1, 11, REG1; \
205 andn REG2, 0x3, REG2; \
206 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
207 brz,pn REG1, FAIL_LABEL; \
208 sllx VADDR, 64 - PMD_SHIFT, REG2; \
209 srlx REG2, 64 - PAGE_SHIFT, REG2; \
210 sllx REG1, 11, REG1; \
211 andn REG2, 0x7, REG2; \
212 add REG1, REG2, REG1;
213
214/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
215 * If no entry is found, FAIL_LABEL will be branched to. On success
216 * the resulting PTE value will be left in REG1. VADDR is preserved
217 * by this routine.
218 */
219#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
220 sethi %hi(prom_trans), REG1; \
221 or REG1, %lo(prom_trans), REG1; \
22297: ldx [REG1 + 0x00], REG2; \
223 brz,pn REG2, FAIL_LABEL; \
224 nop; \
225 ldx [REG1 + 0x08], REG3; \
226 add REG2, REG3, REG3; \
227 cmp REG2, VADDR; \
228 bgu,pt %xcc, 98f; \
229 cmp VADDR, REG3; \
230 bgeu,pt %xcc, 98f; \
231 ldx [REG1 + 0x10], REG3; \
232 sub VADDR, REG2, REG2; \
233 ba,pt %xcc, 99f; \
234 add REG3, REG2, REG1; \
23598: ba,pt %xcc, 97b; \
236 add REG1, (3 * 8), REG1; \
23799:
238
239 /* We use a 32K TSB for the whole kernel, this allows to
240 * handle about 16MB of modules and vmalloc mappings without
241 * incurring many hash conflicts.
242 */
243#define KERNEL_TSB_SIZE_BYTES (32 * 1024)
244#define KERNEL_TSB_NENTRIES \
245 (KERNEL_TSB_SIZE_BYTES / 16)
246#define KERNEL_TSB4M_NENTRIES 4096
247
248 /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
249 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
250 * and the found TTE will be left in REG1. REG3 and REG4 must
251 * be an even/odd pair of registers.
252 *
253 * VADDR and TAG will be preserved and not clobbered by this macro.
254 */
255#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
256 sethi %hi(swapper_tsb), REG1; \
257 or REG1, %lo(swapper_tsb), REG1; \
258 srlx VADDR, PAGE_SHIFT, REG2; \
259 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
260 sllx REG2, 4, REG2; \
261 add REG1, REG2, REG2; \
262 KTSB_LOAD_QUAD(REG2, REG3); \
263 cmp REG3, TAG; \
264 be,a,pt %xcc, OK_LABEL; \
265 mov REG4, REG1;
266
267#ifndef CONFIG_DEBUG_PAGEALLOC
268 /* This version uses a trick, the TAG is already (VADDR >> 22) so
269 * we can make use of that for the index computation.
270 */
271#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
272 sethi %hi(swapper_4m_tsb), REG1; \
273 or REG1, %lo(swapper_4m_tsb), REG1; \
274 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
275 sllx REG2, 4, REG2; \
276 add REG1, REG2, REG2; \
277 KTSB_LOAD_QUAD(REG2, REG3); \
278 cmp REG3, TAG; \
279 be,a,pt %xcc, OK_LABEL; \
280 mov REG4, REG1;
281#endif
282
283#endif /* !(_SPARC64_TSB_H) */
diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h
index 0ba199587e07..a550f1bf6f9b 100644
--- a/include/asm-sparc64/ttable.h
+++ b/include/asm-sparc64/ttable.h
@@ -1,658 +1 @@
1#ifndef _SPARC64_TTABLE_H #include <asm-sparc/ttable.h>
2#define _SPARC64_TTABLE_H
3
4#include <asm/utrap.h>
5
6#ifdef __ASSEMBLY__
7#include <asm/thread_info.h>
8#endif
9
10#define BOOT_KERNEL b sparc64_boot; nop; nop; nop; nop; nop; nop; nop;
11
12/* We need a "cleaned" instruction... */
13#define CLEAN_WINDOW \
14 rdpr %cleanwin, %l0; add %l0, 1, %l0; \
15 wrpr %l0, 0x0, %cleanwin; \
16 clr %o0; clr %o1; clr %o2; clr %o3; \
17 clr %o4; clr %o5; clr %o6; clr %o7; \
18 clr %l0; clr %l1; clr %l2; clr %l3; \
19 clr %l4; clr %l5; clr %l6; clr %l7; \
20 retry; \
21 nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
22
23#define TRAP(routine) \
24 sethi %hi(109f), %g7; \
25 ba,pt %xcc, etrap; \
26109: or %g7, %lo(109b), %g7; \
27 call routine; \
28 add %sp, PTREGS_OFF, %o0; \
29 ba,pt %xcc, rtrap; \
30 nop; \
31 nop;
32
33#define TRAP_7INSNS(routine) \
34 sethi %hi(109f), %g7; \
35 ba,pt %xcc, etrap; \
36109: or %g7, %lo(109b), %g7; \
37 call routine; \
38 add %sp, PTREGS_OFF, %o0; \
39 ba,pt %xcc, rtrap; \
40 nop;
41
42#define TRAP_SAVEFPU(routine) \
43 sethi %hi(109f), %g7; \
44 ba,pt %xcc, do_fptrap; \
45109: or %g7, %lo(109b), %g7; \
46 call routine; \
47 add %sp, PTREGS_OFF, %o0; \
48 ba,pt %xcc, rtrap; \
49 nop; \
50 nop;
51
52#define TRAP_NOSAVE(routine) \
53 ba,pt %xcc, routine; \
54 nop; \
55 nop; nop; nop; nop; nop; nop;
56
57#define TRAP_NOSAVE_7INSNS(routine) \
58 ba,pt %xcc, routine; \
59 nop; \
60 nop; nop; nop; nop; nop;
61
62#define TRAPTL1(routine) \
63 sethi %hi(109f), %g7; \
64 ba,pt %xcc, etraptl1; \
65109: or %g7, %lo(109b), %g7; \
66 call routine; \
67 add %sp, PTREGS_OFF, %o0; \
68 ba,pt %xcc, rtrap; \
69 nop; \
70 nop;
71
72#define TRAP_ARG(routine, arg) \
73 sethi %hi(109f), %g7; \
74 ba,pt %xcc, etrap; \
75109: or %g7, %lo(109b), %g7; \
76 add %sp, PTREGS_OFF, %o0; \
77 call routine; \
78 mov arg, %o1; \
79 ba,pt %xcc, rtrap; \
80 nop;
81
82#define TRAPTL1_ARG(routine, arg) \
83 sethi %hi(109f), %g7; \
84 ba,pt %xcc, etraptl1; \
85109: or %g7, %lo(109b), %g7; \
86 add %sp, PTREGS_OFF, %o0; \
87 call routine; \
88 mov arg, %o1; \
89 ba,pt %xcc, rtrap; \
90 nop;
91
92#define SYSCALL_TRAP(routine, systbl) \
93 rdpr %pil, %g2; \
94 mov TSTATE_SYSCALL, %g3; \
95 sethi %hi(109f), %g7; \
96 ba,pt %xcc, etrap_syscall; \
97109: or %g7, %lo(109b), %g7; \
98 sethi %hi(systbl), %l7; \
99 ba,pt %xcc, routine; \
100 or %l7, %lo(systbl), %l7;
101
102#define TRAP_UTRAP(handler,lvl) \
103 mov handler, %g3; \
104 ba,pt %xcc, utrap_trap; \
105 mov lvl, %g4; \
106 nop; \
107 nop; \
108 nop; \
109 nop; \
110 nop;
111
112#ifdef CONFIG_COMPAT
113#define LINUX_32BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sys_call_table32)
114#else
115#define LINUX_32BIT_SYSCALL_TRAP BTRAP(0x110)
116#endif
117#define LINUX_64BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall, sys_call_table64)
118#define GETCC_TRAP TRAP(getcc)
119#define SETCC_TRAP TRAP(setcc)
120#define BREAKPOINT_TRAP TRAP(breakpoint_trap)
121
122#ifdef CONFIG_TRACE_IRQFLAGS
123
124#define TRAP_IRQ(routine, level) \
125 rdpr %pil, %g2; \
126 wrpr %g0, 15, %pil; \
127 sethi %hi(1f-4), %g7; \
128 ba,pt %xcc, etrap_irq; \
129 or %g7, %lo(1f-4), %g7; \
130 nop; \
131 nop; \
132 nop; \
133 .subsection 2; \
1341: call trace_hardirqs_off; \
135 nop; \
136 mov level, %o0; \
137 call routine; \
138 add %sp, PTREGS_OFF, %o1; \
139 ba,a,pt %xcc, rtrap_irq; \
140 .previous;
141
142#else
143
144#define TRAP_IRQ(routine, level) \
145 rdpr %pil, %g2; \
146 wrpr %g0, 15, %pil; \
147 ba,pt %xcc, etrap_irq; \
148 rd %pc, %g7; \
149 mov level, %o0; \
150 call routine; \
151 add %sp, PTREGS_OFF, %o1; \
152 ba,a,pt %xcc, rtrap_irq;
153
154#endif
155
156#define TRAP_IVEC TRAP_NOSAVE(do_ivec)
157
158#define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)
159
160#define BTRAPTL1(lvl) TRAPTL1_ARG(bad_trap_tl1, lvl)
161
162#define FLUSH_WINDOW_TRAP \
163 ba,pt %xcc, etrap; \
164 rd %pc, %g7; \
165 flushw; \
166 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1; \
167 add %l1, 4, %l2; \
168 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]; \
169 ba,pt %xcc, rtrap; \
170 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC];
171
172#ifdef CONFIG_KPROBES
173#define KPROBES_TRAP(lvl) TRAP_IRQ(kprobe_trap, lvl)
174#else
175#define KPROBES_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
176#endif
177
178#ifdef CONFIG_KGDB
179#define KGDB_TRAP(lvl) TRAP_IRQ(kgdb_trap, lvl)
180#else
181#define KGDB_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
182#endif
183
184#define SUN4V_ITSB_MISS \
185 ldxa [%g0] ASI_SCRATCHPAD, %g2; \
186 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \
187 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \
188 srlx %g4, 22, %g6; \
189 ba,pt %xcc, sun4v_itsb_miss; \
190 nop; \
191 nop; \
192 nop;
193
194#define SUN4V_DTSB_MISS \
195 ldxa [%g0] ASI_SCRATCHPAD, %g2; \
196 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \
197 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \
198 srlx %g4, 22, %g6; \
199 ba,pt %xcc, sun4v_dtsb_miss; \
200 nop; \
201 nop; \
202 nop;
203
204/* Before touching these macros, you owe it to yourself to go and
205 * see how arch/sparc64/kernel/winfixup.S works... -DaveM
206 *
207 * For the user cases we used to use the %asi register, but
208 * it turns out that the "wr xxx, %asi" costs ~5 cycles, so
209 * now we use immediate ASI loads and stores instead. Kudos
210 * to Greg Onufer for pointing out this performance anomaly.
211 *
212 * Further note that we cannot use the g2, g4, g5, and g7 alternate
213 * globals in the spill routines, check out the save instruction in
214 * arch/sparc64/kernel/etrap.S to see what I mean about g2, and
215 * g4/g5 are the globals which are preserved by etrap processing
216 * for the caller of it. The g7 register is the return pc for
217 * etrap. Finally, g6 is the current thread register so we cannot
218 * us it in the spill handlers either. Most of these rules do not
219 * apply to fill processing, only g6 is not usable.
220 */
221
222/* Normal kernel spill */
223#define SPILL_0_NORMAL \
224 stx %l0, [%sp + STACK_BIAS + 0x00]; \
225 stx %l1, [%sp + STACK_BIAS + 0x08]; \
226 stx %l2, [%sp + STACK_BIAS + 0x10]; \
227 stx %l3, [%sp + STACK_BIAS + 0x18]; \
228 stx %l4, [%sp + STACK_BIAS + 0x20]; \
229 stx %l5, [%sp + STACK_BIAS + 0x28]; \
230 stx %l6, [%sp + STACK_BIAS + 0x30]; \
231 stx %l7, [%sp + STACK_BIAS + 0x38]; \
232 stx %i0, [%sp + STACK_BIAS + 0x40]; \
233 stx %i1, [%sp + STACK_BIAS + 0x48]; \
234 stx %i2, [%sp + STACK_BIAS + 0x50]; \
235 stx %i3, [%sp + STACK_BIAS + 0x58]; \
236 stx %i4, [%sp + STACK_BIAS + 0x60]; \
237 stx %i5, [%sp + STACK_BIAS + 0x68]; \
238 stx %i6, [%sp + STACK_BIAS + 0x70]; \
239 stx %i7, [%sp + STACK_BIAS + 0x78]; \
240 saved; retry; nop; nop; nop; nop; nop; nop; \
241 nop; nop; nop; nop; nop; nop; nop; nop;
242
243#define SPILL_0_NORMAL_ETRAP \
244etrap_kernel_spill: \
245 stx %l0, [%sp + STACK_BIAS + 0x00]; \
246 stx %l1, [%sp + STACK_BIAS + 0x08]; \
247 stx %l2, [%sp + STACK_BIAS + 0x10]; \
248 stx %l3, [%sp + STACK_BIAS + 0x18]; \
249 stx %l4, [%sp + STACK_BIAS + 0x20]; \
250 stx %l5, [%sp + STACK_BIAS + 0x28]; \
251 stx %l6, [%sp + STACK_BIAS + 0x30]; \
252 stx %l7, [%sp + STACK_BIAS + 0x38]; \
253 stx %i0, [%sp + STACK_BIAS + 0x40]; \
254 stx %i1, [%sp + STACK_BIAS + 0x48]; \
255 stx %i2, [%sp + STACK_BIAS + 0x50]; \
256 stx %i3, [%sp + STACK_BIAS + 0x58]; \
257 stx %i4, [%sp + STACK_BIAS + 0x60]; \
258 stx %i5, [%sp + STACK_BIAS + 0x68]; \
259 stx %i6, [%sp + STACK_BIAS + 0x70]; \
260 stx %i7, [%sp + STACK_BIAS + 0x78]; \
261 saved; \
262 sub %g1, 2, %g1; \
263 ba,pt %xcc, etrap_save; \
264 wrpr %g1, %cwp; \
265 nop; nop; nop; nop; nop; nop; nop; nop; \
266 nop; nop; nop; nop;
267
268/* Normal 64bit spill */
269#define SPILL_1_GENERIC(ASI) \
270 add %sp, STACK_BIAS + 0x00, %g1; \
271 stxa %l0, [%g1 + %g0] ASI; \
272 mov 0x08, %g3; \
273 stxa %l1, [%g1 + %g3] ASI; \
274 add %g1, 0x10, %g1; \
275 stxa %l2, [%g1 + %g0] ASI; \
276 stxa %l3, [%g1 + %g3] ASI; \
277 add %g1, 0x10, %g1; \
278 stxa %l4, [%g1 + %g0] ASI; \
279 stxa %l5, [%g1 + %g3] ASI; \
280 add %g1, 0x10, %g1; \
281 stxa %l6, [%g1 + %g0] ASI; \
282 stxa %l7, [%g1 + %g3] ASI; \
283 add %g1, 0x10, %g1; \
284 stxa %i0, [%g1 + %g0] ASI; \
285 stxa %i1, [%g1 + %g3] ASI; \
286 add %g1, 0x10, %g1; \
287 stxa %i2, [%g1 + %g0] ASI; \
288 stxa %i3, [%g1 + %g3] ASI; \
289 add %g1, 0x10, %g1; \
290 stxa %i4, [%g1 + %g0] ASI; \
291 stxa %i5, [%g1 + %g3] ASI; \
292 add %g1, 0x10, %g1; \
293 stxa %i6, [%g1 + %g0] ASI; \
294 stxa %i7, [%g1 + %g3] ASI; \
295 saved; \
296 retry; nop; nop; \
297 b,a,pt %xcc, spill_fixup_dax; \
298 b,a,pt %xcc, spill_fixup_mna; \
299 b,a,pt %xcc, spill_fixup;
300
301#define SPILL_1_GENERIC_ETRAP \
302etrap_user_spill_64bit: \
303 stxa %l0, [%sp + STACK_BIAS + 0x00] %asi; \
304 stxa %l1, [%sp + STACK_BIAS + 0x08] %asi; \
305 stxa %l2, [%sp + STACK_BIAS + 0x10] %asi; \
306 stxa %l3, [%sp + STACK_BIAS + 0x18] %asi; \
307 stxa %l4, [%sp + STACK_BIAS + 0x20] %asi; \
308 stxa %l5, [%sp + STACK_BIAS + 0x28] %asi; \
309 stxa %l6, [%sp + STACK_BIAS + 0x30] %asi; \
310 stxa %l7, [%sp + STACK_BIAS + 0x38] %asi; \
311 stxa %i0, [%sp + STACK_BIAS + 0x40] %asi; \
312 stxa %i1, [%sp + STACK_BIAS + 0x48] %asi; \
313 stxa %i2, [%sp + STACK_BIAS + 0x50] %asi; \
314 stxa %i3, [%sp + STACK_BIAS + 0x58] %asi; \
315 stxa %i4, [%sp + STACK_BIAS + 0x60] %asi; \
316 stxa %i5, [%sp + STACK_BIAS + 0x68] %asi; \
317 stxa %i6, [%sp + STACK_BIAS + 0x70] %asi; \
318 stxa %i7, [%sp + STACK_BIAS + 0x78] %asi; \
319 saved; \
320 sub %g1, 2, %g1; \
321 ba,pt %xcc, etrap_save; \
322 wrpr %g1, %cwp; \
323 nop; nop; nop; nop; nop; \
324 nop; nop; nop; nop; \
325 ba,a,pt %xcc, etrap_spill_fixup_64bit; \
326 ba,a,pt %xcc, etrap_spill_fixup_64bit; \
327 ba,a,pt %xcc, etrap_spill_fixup_64bit;
328
329#define SPILL_1_GENERIC_ETRAP_FIXUP \
330etrap_spill_fixup_64bit: \
331 ldub [%g6 + TI_WSAVED], %g1; \
332 sll %g1, 3, %g3; \
333 add %g6, %g3, %g3; \
334 stx %sp, [%g3 + TI_RWIN_SPTRS]; \
335 sll %g1, 7, %g3; \
336 add %g6, %g3, %g3; \
337 stx %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
338 stx %l1, [%g3 + TI_REG_WINDOW + 0x08]; \
339 stx %l2, [%g3 + TI_REG_WINDOW + 0x10]; \
340 stx %l3, [%g3 + TI_REG_WINDOW + 0x18]; \
341 stx %l4, [%g3 + TI_REG_WINDOW + 0x20]; \
342 stx %l5, [%g3 + TI_REG_WINDOW + 0x28]; \
343 stx %l6, [%g3 + TI_REG_WINDOW + 0x30]; \
344 stx %l7, [%g3 + TI_REG_WINDOW + 0x38]; \
345 stx %i0, [%g3 + TI_REG_WINDOW + 0x40]; \
346 stx %i1, [%g3 + TI_REG_WINDOW + 0x48]; \
347 stx %i2, [%g3 + TI_REG_WINDOW + 0x50]; \
348 stx %i3, [%g3 + TI_REG_WINDOW + 0x58]; \
349 stx %i4, [%g3 + TI_REG_WINDOW + 0x60]; \
350 stx %i5, [%g3 + TI_REG_WINDOW + 0x68]; \
351 stx %i6, [%g3 + TI_REG_WINDOW + 0x70]; \
352 stx %i7, [%g3 + TI_REG_WINDOW + 0x78]; \
353 add %g1, 1, %g1; \
354 stb %g1, [%g6 + TI_WSAVED]; \
355 saved; \
356 rdpr %cwp, %g1; \
357 sub %g1, 2, %g1; \
358 ba,pt %xcc, etrap_save; \
359 wrpr %g1, %cwp; \
360 nop; nop; nop
361
362/* Normal 32bit spill */
363#define SPILL_2_GENERIC(ASI) \
364 srl %sp, 0, %sp; \
365 stwa %l0, [%sp + %g0] ASI; \
366 mov 0x04, %g3; \
367 stwa %l1, [%sp + %g3] ASI; \
368 add %sp, 0x08, %g1; \
369 stwa %l2, [%g1 + %g0] ASI; \
370 stwa %l3, [%g1 + %g3] ASI; \
371 add %g1, 0x08, %g1; \
372 stwa %l4, [%g1 + %g0] ASI; \
373 stwa %l5, [%g1 + %g3] ASI; \
374 add %g1, 0x08, %g1; \
375 stwa %l6, [%g1 + %g0] ASI; \
376 stwa %l7, [%g1 + %g3] ASI; \
377 add %g1, 0x08, %g1; \
378 stwa %i0, [%g1 + %g0] ASI; \
379 stwa %i1, [%g1 + %g3] ASI; \
380 add %g1, 0x08, %g1; \
381 stwa %i2, [%g1 + %g0] ASI; \
382 stwa %i3, [%g1 + %g3] ASI; \
383 add %g1, 0x08, %g1; \
384 stwa %i4, [%g1 + %g0] ASI; \
385 stwa %i5, [%g1 + %g3] ASI; \
386 add %g1, 0x08, %g1; \
387 stwa %i6, [%g1 + %g0] ASI; \
388 stwa %i7, [%g1 + %g3] ASI; \
389 saved; \
390 retry; nop; nop; \
391 b,a,pt %xcc, spill_fixup_dax; \
392 b,a,pt %xcc, spill_fixup_mna; \
393 b,a,pt %xcc, spill_fixup;
394
395#define SPILL_2_GENERIC_ETRAP \
396etrap_user_spill_32bit: \
397 srl %sp, 0, %sp; \
398 stwa %l0, [%sp + 0x00] %asi; \
399 stwa %l1, [%sp + 0x04] %asi; \
400 stwa %l2, [%sp + 0x08] %asi; \
401 stwa %l3, [%sp + 0x0c] %asi; \
402 stwa %l4, [%sp + 0x10] %asi; \
403 stwa %l5, [%sp + 0x14] %asi; \
404 stwa %l6, [%sp + 0x18] %asi; \
405 stwa %l7, [%sp + 0x1c] %asi; \
406 stwa %i0, [%sp + 0x20] %asi; \
407 stwa %i1, [%sp + 0x24] %asi; \
408 stwa %i2, [%sp + 0x28] %asi; \
409 stwa %i3, [%sp + 0x2c] %asi; \
410 stwa %i4, [%sp + 0x30] %asi; \
411 stwa %i5, [%sp + 0x34] %asi; \
412 stwa %i6, [%sp + 0x38] %asi; \
413 stwa %i7, [%sp + 0x3c] %asi; \
414 saved; \
415 sub %g1, 2, %g1; \
416 ba,pt %xcc, etrap_save; \
417 wrpr %g1, %cwp; \
418 nop; nop; nop; nop; \
419 nop; nop; nop; nop; \
420 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
421 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
422 ba,a,pt %xcc, etrap_spill_fixup_32bit;
423
424#define SPILL_2_GENERIC_ETRAP_FIXUP \
425etrap_spill_fixup_32bit: \
426 ldub [%g6 + TI_WSAVED], %g1; \
427 sll %g1, 3, %g3; \
428 add %g6, %g3, %g3; \
429 stx %sp, [%g3 + TI_RWIN_SPTRS]; \
430 sll %g1, 7, %g3; \
431 add %g6, %g3, %g3; \
432 stw %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
433 stw %l1, [%g3 + TI_REG_WINDOW + 0x04]; \
434 stw %l2, [%g3 + TI_REG_WINDOW + 0x08]; \
435 stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]; \
436 stw %l4, [%g3 + TI_REG_WINDOW + 0x10]; \
437 stw %l5, [%g3 + TI_REG_WINDOW + 0x14]; \
438 stw %l6, [%g3 + TI_REG_WINDOW + 0x18]; \
439 stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]; \
440 stw %i0, [%g3 + TI_REG_WINDOW + 0x20]; \
441 stw %i1, [%g3 + TI_REG_WINDOW + 0x24]; \
442 stw %i2, [%g3 + TI_REG_WINDOW + 0x28]; \
443 stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]; \
444 stw %i4, [%g3 + TI_REG_WINDOW + 0x30]; \
445 stw %i5, [%g3 + TI_REG_WINDOW + 0x34]; \
446 stw %i6, [%g3 + TI_REG_WINDOW + 0x38]; \
447 stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]; \
448 add %g1, 1, %g1; \
449 stb %g1, [%g6 + TI_WSAVED]; \
450 saved; \
451 rdpr %cwp, %g1; \
452 sub %g1, 2, %g1; \
453 ba,pt %xcc, etrap_save; \
454 wrpr %g1, %cwp; \
455 nop; nop; nop
456
457#define SPILL_1_NORMAL SPILL_1_GENERIC(ASI_AIUP)
458#define SPILL_2_NORMAL SPILL_2_GENERIC(ASI_AIUP)
459#define SPILL_3_NORMAL SPILL_0_NORMAL
460#define SPILL_4_NORMAL SPILL_0_NORMAL
461#define SPILL_5_NORMAL SPILL_0_NORMAL
462#define SPILL_6_NORMAL SPILL_0_NORMAL
463#define SPILL_7_NORMAL SPILL_0_NORMAL
464
465#define SPILL_0_OTHER SPILL_0_NORMAL
466#define SPILL_1_OTHER SPILL_1_GENERIC(ASI_AIUS)
467#define SPILL_2_OTHER SPILL_2_GENERIC(ASI_AIUS)
468#define SPILL_3_OTHER SPILL_3_NORMAL
469#define SPILL_4_OTHER SPILL_4_NORMAL
470#define SPILL_5_OTHER SPILL_5_NORMAL
471#define SPILL_6_OTHER SPILL_6_NORMAL
472#define SPILL_7_OTHER SPILL_7_NORMAL
473
474/* Normal kernel fill */
475#define FILL_0_NORMAL \
476 ldx [%sp + STACK_BIAS + 0x00], %l0; \
477 ldx [%sp + STACK_BIAS + 0x08], %l1; \
478 ldx [%sp + STACK_BIAS + 0x10], %l2; \
479 ldx [%sp + STACK_BIAS + 0x18], %l3; \
480 ldx [%sp + STACK_BIAS + 0x20], %l4; \
481 ldx [%sp + STACK_BIAS + 0x28], %l5; \
482 ldx [%sp + STACK_BIAS + 0x30], %l6; \
483 ldx [%sp + STACK_BIAS + 0x38], %l7; \
484 ldx [%sp + STACK_BIAS + 0x40], %i0; \
485 ldx [%sp + STACK_BIAS + 0x48], %i1; \
486 ldx [%sp + STACK_BIAS + 0x50], %i2; \
487 ldx [%sp + STACK_BIAS + 0x58], %i3; \
488 ldx [%sp + STACK_BIAS + 0x60], %i4; \
489 ldx [%sp + STACK_BIAS + 0x68], %i5; \
490 ldx [%sp + STACK_BIAS + 0x70], %i6; \
491 ldx [%sp + STACK_BIAS + 0x78], %i7; \
492 restored; retry; nop; nop; nop; nop; nop; nop; \
493 nop; nop; nop; nop; nop; nop; nop; nop;
494
495#define FILL_0_NORMAL_RTRAP \
496kern_rtt_fill: \
497 rdpr %cwp, %g1; \
498 sub %g1, 1, %g1; \
499 wrpr %g1, %cwp; \
500 ldx [%sp + STACK_BIAS + 0x00], %l0; \
501 ldx [%sp + STACK_BIAS + 0x08], %l1; \
502 ldx [%sp + STACK_BIAS + 0x10], %l2; \
503 ldx [%sp + STACK_BIAS + 0x18], %l3; \
504 ldx [%sp + STACK_BIAS + 0x20], %l4; \
505 ldx [%sp + STACK_BIAS + 0x28], %l5; \
506 ldx [%sp + STACK_BIAS + 0x30], %l6; \
507 ldx [%sp + STACK_BIAS + 0x38], %l7; \
508 ldx [%sp + STACK_BIAS + 0x40], %i0; \
509 ldx [%sp + STACK_BIAS + 0x48], %i1; \
510 ldx [%sp + STACK_BIAS + 0x50], %i2; \
511 ldx [%sp + STACK_BIAS + 0x58], %i3; \
512 ldx [%sp + STACK_BIAS + 0x60], %i4; \
513 ldx [%sp + STACK_BIAS + 0x68], %i5; \
514 ldx [%sp + STACK_BIAS + 0x70], %i6; \
515 ldx [%sp + STACK_BIAS + 0x78], %i7; \
516 restored; \
517 add %g1, 1, %g1; \
518 ba,pt %xcc, kern_rtt_restore; \
519 wrpr %g1, %cwp; \
520 nop; nop; nop; nop; nop; \
521 nop; nop; nop; nop;
522
523
524/* Normal 64bit fill */
525#define FILL_1_GENERIC(ASI) \
526 add %sp, STACK_BIAS + 0x00, %g1; \
527 ldxa [%g1 + %g0] ASI, %l0; \
528 mov 0x08, %g2; \
529 mov 0x10, %g3; \
530 ldxa [%g1 + %g2] ASI, %l1; \
531 mov 0x18, %g5; \
532 ldxa [%g1 + %g3] ASI, %l2; \
533 ldxa [%g1 + %g5] ASI, %l3; \
534 add %g1, 0x20, %g1; \
535 ldxa [%g1 + %g0] ASI, %l4; \
536 ldxa [%g1 + %g2] ASI, %l5; \
537 ldxa [%g1 + %g3] ASI, %l6; \
538 ldxa [%g1 + %g5] ASI, %l7; \
539 add %g1, 0x20, %g1; \
540 ldxa [%g1 + %g0] ASI, %i0; \
541 ldxa [%g1 + %g2] ASI, %i1; \
542 ldxa [%g1 + %g3] ASI, %i2; \
543 ldxa [%g1 + %g5] ASI, %i3; \
544 add %g1, 0x20, %g1; \
545 ldxa [%g1 + %g0] ASI, %i4; \
546 ldxa [%g1 + %g2] ASI, %i5; \
547 ldxa [%g1 + %g3] ASI, %i6; \
548 ldxa [%g1 + %g5] ASI, %i7; \
549 restored; \
550 retry; nop; nop; nop; nop; \
551 b,a,pt %xcc, fill_fixup_dax; \
552 b,a,pt %xcc, fill_fixup_mna; \
553 b,a,pt %xcc, fill_fixup;
554
555#define FILL_1_GENERIC_RTRAP \
556user_rtt_fill_64bit: \
557 ldxa [%sp + STACK_BIAS + 0x00] %asi, %l0; \
558 ldxa [%sp + STACK_BIAS + 0x08] %asi, %l1; \
559 ldxa [%sp + STACK_BIAS + 0x10] %asi, %l2; \
560 ldxa [%sp + STACK_BIAS + 0x18] %asi, %l3; \
561 ldxa [%sp + STACK_BIAS + 0x20] %asi, %l4; \
562 ldxa [%sp + STACK_BIAS + 0x28] %asi, %l5; \
563 ldxa [%sp + STACK_BIAS + 0x30] %asi, %l6; \
564 ldxa [%sp + STACK_BIAS + 0x38] %asi, %l7; \
565 ldxa [%sp + STACK_BIAS + 0x40] %asi, %i0; \
566 ldxa [%sp + STACK_BIAS + 0x48] %asi, %i1; \
567 ldxa [%sp + STACK_BIAS + 0x50] %asi, %i2; \
568 ldxa [%sp + STACK_BIAS + 0x58] %asi, %i3; \
569 ldxa [%sp + STACK_BIAS + 0x60] %asi, %i4; \
570 ldxa [%sp + STACK_BIAS + 0x68] %asi, %i5; \
571 ldxa [%sp + STACK_BIAS + 0x70] %asi, %i6; \
572 ldxa [%sp + STACK_BIAS + 0x78] %asi, %i7; \
573 ba,pt %xcc, user_rtt_pre_restore; \
574 restored; \
575 nop; nop; nop; nop; nop; nop; \
576 nop; nop; nop; nop; nop; \
577 ba,a,pt %xcc, user_rtt_fill_fixup; \
578 ba,a,pt %xcc, user_rtt_fill_fixup; \
579 ba,a,pt %xcc, user_rtt_fill_fixup;
580
581
582/* Normal 32bit fill */
583#define FILL_2_GENERIC(ASI) \
584 srl %sp, 0, %sp; \
585 lduwa [%sp + %g0] ASI, %l0; \
586 mov 0x04, %g2; \
587 mov 0x08, %g3; \
588 lduwa [%sp + %g2] ASI, %l1; \
589 mov 0x0c, %g5; \
590 lduwa [%sp + %g3] ASI, %l2; \
591 lduwa [%sp + %g5] ASI, %l3; \
592 add %sp, 0x10, %g1; \
593 lduwa [%g1 + %g0] ASI, %l4; \
594 lduwa [%g1 + %g2] ASI, %l5; \
595 lduwa [%g1 + %g3] ASI, %l6; \
596 lduwa [%g1 + %g5] ASI, %l7; \
597 add %g1, 0x10, %g1; \
598 lduwa [%g1 + %g0] ASI, %i0; \
599 lduwa [%g1 + %g2] ASI, %i1; \
600 lduwa [%g1 + %g3] ASI, %i2; \
601 lduwa [%g1 + %g5] ASI, %i3; \
602 add %g1, 0x10, %g1; \
603 lduwa [%g1 + %g0] ASI, %i4; \
604 lduwa [%g1 + %g2] ASI, %i5; \
605 lduwa [%g1 + %g3] ASI, %i6; \
606 lduwa [%g1 + %g5] ASI, %i7; \
607 restored; \
608 retry; nop; nop; nop; nop; \
609 b,a,pt %xcc, fill_fixup_dax; \
610 b,a,pt %xcc, fill_fixup_mna; \
611 b,a,pt %xcc, fill_fixup;
612
613#define FILL_2_GENERIC_RTRAP \
614user_rtt_fill_32bit: \
615 srl %sp, 0, %sp; \
616 lduwa [%sp + 0x00] %asi, %l0; \
617 lduwa [%sp + 0x04] %asi, %l1; \
618 lduwa [%sp + 0x08] %asi, %l2; \
619 lduwa [%sp + 0x0c] %asi, %l3; \
620 lduwa [%sp + 0x10] %asi, %l4; \
621 lduwa [%sp + 0x14] %asi, %l5; \
622 lduwa [%sp + 0x18] %asi, %l6; \
623 lduwa [%sp + 0x1c] %asi, %l7; \
624 lduwa [%sp + 0x20] %asi, %i0; \
625 lduwa [%sp + 0x24] %asi, %i1; \
626 lduwa [%sp + 0x28] %asi, %i2; \
627 lduwa [%sp + 0x2c] %asi, %i3; \
628 lduwa [%sp + 0x30] %asi, %i4; \
629 lduwa [%sp + 0x34] %asi, %i5; \
630 lduwa [%sp + 0x38] %asi, %i6; \
631 lduwa [%sp + 0x3c] %asi, %i7; \
632 ba,pt %xcc, user_rtt_pre_restore; \
633 restored; \
634 nop; nop; nop; nop; nop; \
635 nop; nop; nop; nop; nop; \
636 ba,a,pt %xcc, user_rtt_fill_fixup; \
637 ba,a,pt %xcc, user_rtt_fill_fixup; \
638 ba,a,pt %xcc, user_rtt_fill_fixup;
639
640
641#define FILL_1_NORMAL FILL_1_GENERIC(ASI_AIUP)
642#define FILL_2_NORMAL FILL_2_GENERIC(ASI_AIUP)
643#define FILL_3_NORMAL FILL_0_NORMAL
644#define FILL_4_NORMAL FILL_0_NORMAL
645#define FILL_5_NORMAL FILL_0_NORMAL
646#define FILL_6_NORMAL FILL_0_NORMAL
647#define FILL_7_NORMAL FILL_0_NORMAL
648
649#define FILL_0_OTHER FILL_0_NORMAL
650#define FILL_1_OTHER FILL_1_GENERIC(ASI_AIUS)
651#define FILL_2_OTHER FILL_2_GENERIC(ASI_AIUS)
652#define FILL_3_OTHER FILL_3_NORMAL
653#define FILL_4_OTHER FILL_4_NORMAL
654#define FILL_5_OTHER FILL_5_NORMAL
655#define FILL_6_OTHER FILL_6_NORMAL
656#define FILL_7_OTHER FILL_7_NORMAL
657
658#endif /* !(_SPARC64_TTABLE_H) */
diff --git a/include/asm-sparc64/upa.h b/include/asm-sparc64/upa.h
index 5b1633223f92..aab72930815a 100644
--- a/include/asm-sparc64/upa.h
+++ b/include/asm-sparc64/upa.h
@@ -1,109 +1 @@
1#ifndef _SPARC64_UPA_H #include <asm-sparc/upa.h>
2#define _SPARC64_UPA_H
3
4#include <asm/asi.h>
5
6/* UPA level registers and defines. */
7
8/* UPA Config Register */
9#define UPA_CONFIG_RESV 0xffffffffc0000000 /* Reserved. */
10#define UPA_CONFIG_PCON 0x000000003fc00000 /* Depth of various sys queues. */
11#define UPA_CONFIG_MID 0x00000000003e0000 /* Module ID. */
12#define UPA_CONFIG_PCAP 0x000000000001ffff /* Port Capabilities. */
13
14/* UPA Port ID Register */
15#define UPA_PORTID_FNP 0xff00000000000000 /* Hardcoded to 0xfc on ultra. */
16#define UPA_PORTID_RESV 0x00fffff800000000 /* Reserved. */
17#define UPA_PORTID_ECCVALID 0x0000000400000000 /* Zero if mod can generate ECC */
18#define UPA_PORTID_ONEREAD 0x0000000200000000 /* Set if mod generates P_RASB */
19#define UPA_PORTID_PINTRDQ 0x0000000180000000 /* # outstanding P_INT_REQ's */
20#define UPA_PORTID_PREQDQ 0x000000007e000000 /* slave-wr's to mod supported */
21#define UPA_PORTID_PREQRD 0x0000000001e00000 /* # incoming P_REQ's supported */
22#define UPA_PORTID_UPACAP 0x00000000001f0000 /* UPA capabilities of mod */
23#define UPA_PORTID_ID 0x000000000000ffff /* Module Identification bits */
24
25/* UPA I/O space accessors */
26#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
27static inline unsigned char _upa_readb(unsigned long addr)
28{
29 unsigned char ret;
30
31 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* upa_readb */"
32 : "=r" (ret)
33 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
34
35 return ret;
36}
37
38static inline unsigned short _upa_readw(unsigned long addr)
39{
40 unsigned short ret;
41
42 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* upa_readw */"
43 : "=r" (ret)
44 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
45
46 return ret;
47}
48
49static inline unsigned int _upa_readl(unsigned long addr)
50{
51 unsigned int ret;
52
53 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* upa_readl */"
54 : "=r" (ret)
55 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
56
57 return ret;
58}
59
60static inline unsigned long _upa_readq(unsigned long addr)
61{
62 unsigned long ret;
63
64 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* upa_readq */"
65 : "=r" (ret)
66 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
67
68 return ret;
69}
70
71static inline void _upa_writeb(unsigned char b, unsigned long addr)
72{
73 __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */"
74 : /* no outputs */
75 : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
76}
77
78static inline void _upa_writew(unsigned short w, unsigned long addr)
79{
80 __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */"
81 : /* no outputs */
82 : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
83}
84
85static inline void _upa_writel(unsigned int l, unsigned long addr)
86{
87 __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */"
88 : /* no outputs */
89 : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
90}
91
92static inline void _upa_writeq(unsigned long q, unsigned long addr)
93{
94 __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */"
95 : /* no outputs */
96 : "r" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
97}
98
99#define upa_readb(__addr) (_upa_readb((unsigned long)(__addr)))
100#define upa_readw(__addr) (_upa_readw((unsigned long)(__addr)))
101#define upa_readl(__addr) (_upa_readl((unsigned long)(__addr)))
102#define upa_readq(__addr) (_upa_readq((unsigned long)(__addr)))
103#define upa_writeb(__b, __addr) (_upa_writeb((__b), (unsigned long)(__addr)))
104#define upa_writew(__w, __addr) (_upa_writew((__w), (unsigned long)(__addr)))
105#define upa_writel(__l, __addr) (_upa_writel((__l), (unsigned long)(__addr)))
106#define upa_writeq(__q, __addr) (_upa_writeq((__q), (unsigned long)(__addr)))
107#endif /* __KERNEL__ && !__ASSEMBLY__ */
108
109#endif /* !(_SPARC64_UPA_H) */
diff --git a/include/asm-sparc64/vio.h b/include/asm-sparc64/vio.h
index d4de32f0f8af..299b26ab81a7 100644
--- a/include/asm-sparc64/vio.h
+++ b/include/asm-sparc64/vio.h
@@ -1,406 +1 @@
1#ifndef _SPARC64_VIO_H #include <asm-sparc/vio.h>
2#define _SPARC64_VIO_H
3
4#include <linux/kernel.h>
5#include <linux/device.h>
6#include <linux/mod_devicetable.h>
7#include <linux/timer.h>
8#include <linux/spinlock.h>
9#include <linux/completion.h>
10#include <linux/list.h>
11#include <linux/log2.h>
12
13#include <asm/ldc.h>
14#include <asm/mdesc.h>
15
16struct vio_msg_tag {
17 u8 type;
18#define VIO_TYPE_CTRL 0x01
19#define VIO_TYPE_DATA 0x02
20#define VIO_TYPE_ERR 0x04
21
22 u8 stype;
23#define VIO_SUBTYPE_INFO 0x01
24#define VIO_SUBTYPE_ACK 0x02
25#define VIO_SUBTYPE_NACK 0x04
26
27 u16 stype_env;
28#define VIO_VER_INFO 0x0001
29#define VIO_ATTR_INFO 0x0002
30#define VIO_DRING_REG 0x0003
31#define VIO_DRING_UNREG 0x0004
32#define VIO_RDX 0x0005
33#define VIO_PKT_DATA 0x0040
34#define VIO_DESC_DATA 0x0041
35#define VIO_DRING_DATA 0x0042
36#define VNET_MCAST_INFO 0x0101
37
38 u32 sid;
39};
40
41struct vio_rdx {
42 struct vio_msg_tag tag;
43 u64 resv[6];
44};
45
46struct vio_ver_info {
47 struct vio_msg_tag tag;
48 u16 major;
49 u16 minor;
50 u8 dev_class;
51#define VDEV_NETWORK 0x01
52#define VDEV_NETWORK_SWITCH 0x02
53#define VDEV_DISK 0x03
54#define VDEV_DISK_SERVER 0x04
55
56 u8 resv1[3];
57 u64 resv2[5];
58};
59
60struct vio_dring_register {
61 struct vio_msg_tag tag;
62 u64 dring_ident;
63 u32 num_descr;
64 u32 descr_size;
65 u16 options;
66#define VIO_TX_DRING 0x0001
67#define VIO_RX_DRING 0x0002
68 u16 resv;
69 u32 num_cookies;
70 struct ldc_trans_cookie cookies[0];
71};
72
73struct vio_dring_unregister {
74 struct vio_msg_tag tag;
75 u64 dring_ident;
76 u64 resv[5];
77};
78
79/* Data transfer modes */
80#define VIO_PKT_MODE 0x01 /* Packet based transfer */
81#define VIO_DESC_MODE 0x02 /* In-band descriptors */
82#define VIO_DRING_MODE 0x03 /* Descriptor rings */
83
84struct vio_dring_data {
85 struct vio_msg_tag tag;
86 u64 seq;
87 u64 dring_ident;
88 u32 start_idx;
89 u32 end_idx;
90 u8 state;
91#define VIO_DRING_ACTIVE 0x01
92#define VIO_DRING_STOPPED 0x02
93
94 u8 __pad1;
95 u16 __pad2;
96 u32 __pad3;
97 u64 __par4[2];
98};
99
100struct vio_dring_hdr {
101 u8 state;
102#define VIO_DESC_FREE 0x01
103#define VIO_DESC_READY 0x02
104#define VIO_DESC_ACCEPTED 0x03
105#define VIO_DESC_DONE 0x04
106 u8 ack;
107#define VIO_ACK_ENABLE 0x01
108#define VIO_ACK_DISABLE 0x00
109
110 u16 __pad1;
111 u32 __pad2;
112};
113
114/* VIO disk specific structures and defines */
115struct vio_disk_attr_info {
116 struct vio_msg_tag tag;
117 u8 xfer_mode;
118 u8 vdisk_type;
119#define VD_DISK_TYPE_SLICE 0x01 /* Slice in block device */
120#define VD_DISK_TYPE_DISK 0x02 /* Entire block device */
121 u16 resv1;
122 u32 vdisk_block_size;
123 u64 operations;
124 u64 vdisk_size;
125 u64 max_xfer_size;
126 u64 resv2[2];
127};
128
129struct vio_disk_desc {
130 struct vio_dring_hdr hdr;
131 u64 req_id;
132 u8 operation;
133#define VD_OP_BREAD 0x01 /* Block read */
134#define VD_OP_BWRITE 0x02 /* Block write */
135#define VD_OP_FLUSH 0x03 /* Flush disk contents */
136#define VD_OP_GET_WCE 0x04 /* Get write-cache status */
137#define VD_OP_SET_WCE 0x05 /* Enable/disable write-cache */
138#define VD_OP_GET_VTOC 0x06 /* Get VTOC */
139#define VD_OP_SET_VTOC 0x07 /* Set VTOC */
140#define VD_OP_GET_DISKGEOM 0x08 /* Get disk geometry */
141#define VD_OP_SET_DISKGEOM 0x09 /* Set disk geometry */
142#define VD_OP_SCSICMD 0x0a /* SCSI control command */
143#define VD_OP_GET_DEVID 0x0b /* Get device ID */
144#define VD_OP_GET_EFI 0x0c /* Get EFI */
145#define VD_OP_SET_EFI 0x0d /* Set EFI */
146 u8 slice;
147 u16 resv1;
148 u32 status;
149 u64 offset;
150 u64 size;
151 u32 ncookies;
152 u32 resv2;
153 struct ldc_trans_cookie cookies[0];
154};
155
156#define VIO_DISK_VNAME_LEN 8
157#define VIO_DISK_ALABEL_LEN 128
158#define VIO_DISK_NUM_PART 8
159
160struct vio_disk_vtoc {
161 u8 volume_name[VIO_DISK_VNAME_LEN];
162 u16 sector_size;
163 u16 num_partitions;
164 u8 ascii_label[VIO_DISK_ALABEL_LEN];
165 struct {
166 u16 id;
167 u16 perm_flags;
168 u32 resv;
169 u64 start_block;
170 u64 num_blocks;
171 } partitions[VIO_DISK_NUM_PART];
172};
173
174struct vio_disk_geom {
175 u16 num_cyl; /* Num data cylinders */
176 u16 alt_cyl; /* Num alternate cylinders */
177 u16 beg_cyl; /* Cyl off of fixed head area */
178 u16 num_hd; /* Num heads */
179 u16 num_sec; /* Num sectors */
180 u16 ifact; /* Interleave factor */
181 u16 apc; /* Alts per cylinder (SCSI) */
182 u16 rpm; /* Revolutions per minute */
183 u16 phy_cyl; /* Num physical cylinders */
184 u16 wr_skip; /* Num sects to skip, writes */
185 u16 rd_skip; /* Num sects to skip, writes */
186};
187
188struct vio_disk_devid {
189 u16 resv;
190 u16 type;
191 u32 len;
192 char id[0];
193};
194
195struct vio_disk_efi {
196 u64 lba;
197 u64 len;
198 char data[0];
199};
200
201/* VIO net specific structures and defines */
202struct vio_net_attr_info {
203 struct vio_msg_tag tag;
204 u8 xfer_mode;
205 u8 addr_type;
206#define VNET_ADDR_ETHERMAC 0x01
207 u16 ack_freq;
208 u32 resv1;
209 u64 addr;
210 u64 mtu;
211 u64 resv2[3];
212};
213
214#define VNET_NUM_MCAST 7
215
216struct vio_net_mcast_info {
217 struct vio_msg_tag tag;
218 u8 set;
219 u8 count;
220 u8 mcast_addr[VNET_NUM_MCAST * 6];
221 u32 resv;
222};
223
224struct vio_net_desc {
225 struct vio_dring_hdr hdr;
226 u32 size;
227 u32 ncookies;
228 struct ldc_trans_cookie cookies[0];
229};
230
231#define VIO_MAX_RING_COOKIES 24
232
233struct vio_dring_state {
234 u64 ident;
235 void *base;
236 u64 snd_nxt;
237 u64 rcv_nxt;
238 u32 entry_size;
239 u32 num_entries;
240 u32 prod;
241 u32 cons;
242 u32 pending;
243 int ncookies;
244 struct ldc_trans_cookie cookies[VIO_MAX_RING_COOKIES];
245};
246
247static inline void *vio_dring_cur(struct vio_dring_state *dr)
248{
249 return dr->base + (dr->entry_size * dr->prod);
250}
251
252static inline void *vio_dring_entry(struct vio_dring_state *dr,
253 unsigned int index)
254{
255 return dr->base + (dr->entry_size * index);
256}
257
258static inline u32 vio_dring_avail(struct vio_dring_state *dr,
259 unsigned int ring_size)
260{
261 BUILD_BUG_ON(!is_power_of_2(ring_size));
262
263 return (dr->pending -
264 ((dr->prod - dr->cons) & (ring_size - 1)));
265}
266
267#define VIO_MAX_TYPE_LEN 32
268#define VIO_MAX_COMPAT_LEN 64
269
270struct vio_dev {
271 u64 mp;
272 struct device_node *dp;
273
274 char type[VIO_MAX_TYPE_LEN];
275 char compat[VIO_MAX_COMPAT_LEN];
276 int compat_len;
277
278 u64 dev_no;
279
280 unsigned long channel_id;
281
282 unsigned int tx_irq;
283 unsigned int rx_irq;
284
285 struct device dev;
286};
287
288struct vio_driver {
289 struct list_head node;
290 const struct vio_device_id *id_table;
291 int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
292 int (*remove)(struct vio_dev *dev);
293 void (*shutdown)(struct vio_dev *dev);
294 unsigned long driver_data;
295 struct device_driver driver;
296};
297
298struct vio_version {
299 u16 major;
300 u16 minor;
301};
302
303struct vio_driver_state;
304struct vio_driver_ops {
305 int (*send_attr)(struct vio_driver_state *vio);
306 int (*handle_attr)(struct vio_driver_state *vio, void *pkt);
307 void (*handshake_complete)(struct vio_driver_state *vio);
308};
309
310struct vio_completion {
311 struct completion com;
312 int err;
313 int waiting_for;
314};
315
316struct vio_driver_state {
317 /* Protects VIO handshake and, optionally, driver private state. */
318 spinlock_t lock;
319
320 struct ldc_channel *lp;
321
322 u32 _peer_sid;
323 u32 _local_sid;
324 struct vio_dring_state drings[2];
325#define VIO_DRIVER_TX_RING 0
326#define VIO_DRIVER_RX_RING 1
327
328 u8 hs_state;
329#define VIO_HS_INVALID 0x00
330#define VIO_HS_GOTVERS 0x01
331#define VIO_HS_GOT_ATTR 0x04
332#define VIO_HS_SENT_DREG 0x08
333#define VIO_HS_SENT_RDX 0x10
334#define VIO_HS_GOT_RDX_ACK 0x20
335#define VIO_HS_GOT_RDX 0x40
336#define VIO_HS_SENT_RDX_ACK 0x80
337#define VIO_HS_COMPLETE (VIO_HS_GOT_RDX_ACK | VIO_HS_SENT_RDX_ACK)
338
339 u8 dev_class;
340
341 u8 dr_state;
342#define VIO_DR_STATE_TXREG 0x01
343#define VIO_DR_STATE_RXREG 0x02
344#define VIO_DR_STATE_TXREQ 0x10
345#define VIO_DR_STATE_RXREQ 0x20
346
347 u8 debug;
348#define VIO_DEBUG_HS 0x01
349#define VIO_DEBUG_DATA 0x02
350
351 void *desc_buf;
352 unsigned int desc_buf_len;
353
354 struct vio_completion *cmp;
355
356 struct vio_dev *vdev;
357
358 struct timer_list timer;
359
360 struct vio_version ver;
361
362 struct vio_version *ver_table;
363 int ver_table_entries;
364
365 char *name;
366
367 struct vio_driver_ops *ops;
368};
369
370#define viodbg(TYPE, f, a...) \
371do { if (vio->debug & VIO_DEBUG_##TYPE) \
372 printk(KERN_INFO "vio: ID[%lu] " f, \
373 vio->vdev->channel_id, ## a); \
374} while (0)
375
376extern int vio_register_driver(struct vio_driver *drv);
377extern void vio_unregister_driver(struct vio_driver *drv);
378
379static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
380{
381 return container_of(drv, struct vio_driver, driver);
382}
383
384static inline struct vio_dev *to_vio_dev(struct device *dev)
385{
386 return container_of(dev, struct vio_dev, dev);
387}
388
389extern int vio_ldc_send(struct vio_driver_state *vio, void *data, int len);
390extern void vio_link_state_change(struct vio_driver_state *vio, int event);
391extern void vio_conn_reset(struct vio_driver_state *vio);
392extern int vio_control_pkt_engine(struct vio_driver_state *vio, void *pkt);
393extern int vio_validate_sid(struct vio_driver_state *vio,
394 struct vio_msg_tag *tp);
395extern u32 vio_send_sid(struct vio_driver_state *vio);
396extern int vio_ldc_alloc(struct vio_driver_state *vio,
397 struct ldc_channel_config *base_cfg, void *event_arg);
398extern void vio_ldc_free(struct vio_driver_state *vio);
399extern int vio_driver_init(struct vio_driver_state *vio, struct vio_dev *vdev,
400 u8 dev_class, struct vio_version *ver_table,
401 int ver_table_size, struct vio_driver_ops *ops,
402 char *name);
403
404extern void vio_port_up(struct vio_driver_state *vio);
405
406#endif /* _SPARC64_VIO_H */
diff --git a/include/asm-sparc64/visasm.h b/include/asm-sparc64/visasm.h
index 34f2ec64933b..837a12278f4a 100644
--- a/include/asm-sparc64/visasm.h
+++ b/include/asm-sparc64/visasm.h
@@ -1,62 +1 @@
1#ifndef _SPARC64_VISASM_H #include <asm-sparc/visasm.h>
2#define _SPARC64_VISASM_H
3
4/* visasm.h: FPU saving macros for VIS routines
5 *
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
7 */
8
9#include <asm/pstate.h>
10#include <asm/ptrace.h>
11
12/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
13
14#define VISEntry \
15 rd %fprs, %o5; \
16 andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
17 be,pt %icc, 297f; \
18 sethi %hi(297f), %g7; \
19 sethi %hi(VISenter), %g1; \
20 jmpl %g1 + %lo(VISenter), %g0; \
21 or %g7, %lo(297f), %g7; \
22297: wr %g0, FPRS_FEF, %fprs; \
23
24#define VISExit \
25 wr %g0, 0, %fprs;
26
27/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
28 * Must preserve %o5 between VISEntryHalf and VISExitHalf */
29
30#define VISEntryHalf \
31 rd %fprs, %o5; \
32 andcc %o5, FPRS_FEF, %g0; \
33 be,pt %icc, 297f; \
34 sethi %hi(298f), %g7; \
35 sethi %hi(VISenterhalf), %g1; \
36 jmpl %g1 + %lo(VISenterhalf), %g0; \
37 or %g7, %lo(298f), %g7; \
38 clr %o5; \
39297: wr %o5, FPRS_FEF, %fprs; \
40298:
41
42#define VISExitHalf \
43 wr %o5, 0, %fprs;
44
45#ifndef __ASSEMBLY__
46static inline void save_and_clear_fpu(void) {
47 __asm__ __volatile__ (
48" rd %%fprs, %%o5\n"
49" andcc %%o5, %0, %%g0\n"
50" be,pt %%icc, 299f\n"
51" sethi %%hi(298f), %%g7\n"
52" sethi %%hi(VISenter), %%g1\n"
53" jmpl %%g1 + %%lo(VISenter), %%g0\n"
54" or %%g7, %%lo(298f), %%g7\n"
55" 298: wr %%g0, 0, %%fprs\n"
56" 299:\n"
57" " : : "i" (FPRS_FEF|FPRS_DU) :
58 "o5", "g1", "g2", "g3", "g7", "cc");
59}
60#endif
61
62#endif /* _SPARC64_ASI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 17:22:09 -0500