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authorDavid S. Miller <davem@sunset.davemloft.net>2005-10-14 01:15:24 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2005-10-14 01:15:24 -0400
commit688cb30bdc3e398d97682a6a58f825821ee838c2 (patch)
tree8fc9ca543fc3966eb961743ba4587298fce49279 /include/asm-sparc64
parent51e8513615ed8202b22ba9a43b0c7376ea4f6868 (diff)
[SPARC64]: Eliminate PCI IOMMU dma mapping size limit.
The hairy fast allocator in the sparc64 PCI IOMMU code has a hard limit of 256 pages. Certain devices can exceed this when performing very large I/Os. So replace with a more simple allocator, based largely upon the arch/ppc64/kernel/iommu.c code. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64')
-rw-r--r--include/asm-sparc64/pbm.h28
1 files changed, 8 insertions, 20 deletions
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index c067407de0b0..dd35a2c7798a 100644
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -27,23 +27,27 @@
27 * PCI bus. 27 * PCI bus.
28 */ 28 */
29 29
30#define PBM_LOGCLUSTERS 3
31#define PBM_NCLUSTERS (1 << PBM_LOGCLUSTERS)
32
33struct pci_controller_info; 30struct pci_controller_info;
34 31
35/* This contains the software state necessary to drive a PCI 32/* This contains the software state necessary to drive a PCI
36 * controller's IOMMU. 33 * controller's IOMMU.
37 */ 34 */
35struct pci_iommu_arena {
36 unsigned long *map;
37 unsigned int hint;
38 unsigned int limit;
39};
40
38struct pci_iommu { 41struct pci_iommu {
39 /* This protects the controller's IOMMU and all 42 /* This protects the controller's IOMMU and all
40 * streaming buffers underneath. 43 * streaming buffers underneath.
41 */ 44 */
42 spinlock_t lock; 45 spinlock_t lock;
43 46
47 struct pci_iommu_arena arena;
48
44 /* IOMMU page table, a linear array of ioptes. */ 49 /* IOMMU page table, a linear array of ioptes. */
45 iopte_t *page_table; /* The page table itself. */ 50 iopte_t *page_table; /* The page table itself. */
46 int page_table_sz_bits; /* log2 of ow many pages does it map? */
47 51
48 /* Base PCI memory space address where IOMMU mappings 52 /* Base PCI memory space address where IOMMU mappings
49 * begin. 53 * begin.
@@ -62,12 +66,6 @@ struct pci_iommu {
62 */ 66 */
63 unsigned long write_complete_reg; 67 unsigned long write_complete_reg;
64 68
65 /* The lowest used consistent mapping entry. Since
66 * we allocate consistent maps out of cluster 0 this
67 * is relative to the beginning of closter 0.
68 */
69 u32 lowest_consistent_map;
70
71 /* In order to deal with some buggy third-party PCI bridges that 69 /* In order to deal with some buggy third-party PCI bridges that
72 * do wrong prefetching, we never mark valid mappings as invalid. 70 * do wrong prefetching, we never mark valid mappings as invalid.
73 * Instead we point them at this dummy page. 71 * Instead we point them at this dummy page.
@@ -75,16 +73,6 @@ struct pci_iommu {
75 unsigned long dummy_page; 73 unsigned long dummy_page;
76 unsigned long dummy_page_pa; 74 unsigned long dummy_page_pa;
77 75
78 /* If PBM_NCLUSTERS is ever decreased to 4 or lower,
79 * or if largest supported page_table_sz * 8K goes above
80 * 2GB, you must increase the size of the type of
81 * these counters. You have been duly warned. -DaveM
82 */
83 struct {
84 u16 next;
85 u16 flush;
86 } alloc_info[PBM_NCLUSTERS];
87
88 /* CTX allocation. */ 76 /* CTX allocation. */
89 unsigned long ctx_lowest_free; 77 unsigned long ctx_lowest_free;
90 unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)]; 78 unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];