[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.

Check the cpu type in the OBP device tree before committing to
using the optimized Niagara memcpy and memset implementation.

If we don't recognize the cpu type, use a completely generic
version.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 5 insertions, 1 deletions

diff --git a/include/asm-sparc64/xor.h b/include/asm-sparc64/xor.h
index 8ce3f1813e28..a0233884fc94 100644
--- a/include/asm-sparc64/xor.h
+++ b/include/asm-sparc64/xor.h
@@ -63,4 +63,8 @@ static struct xor_block_template xor_block_niagara = {
 
 /* For VIS for everything except Niagara.  */
 #define XOR_SELECT_TEMPLATE(FASTEST) \
-        (tlb_type == hypervisor ? &xor_block_niagara : &xor_block_VIS)
+        ((tlb_type == hypervisor && \
+          (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
+           sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \
+         &xor_block_niagara : \
+         &xor_block_VIS)