diff options
| author | David S. Miller <davem@sunset.davemloft.net> | 2006-02-17 21:01:02 -0500 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 04:13:34 -0500 |
| commit | 8b234274418d6d79527c4ac3a72da446ca4cb35f (patch) | |
| tree | ab4ab14fa7f1cab7889ecc2339f0261253a5d0e1 /include/asm-sparc64/ttable.h | |
| parent | 7adb37fe80d06cbd40de9b225b12a3a9ec40b6bb (diff) | |
[SPARC64]: More TLB/TSB handling fixes.
The SUN4V convention with non-shared TSBs is that the context
bit of the TAG is clear. So we have to choose an "invalid"
bit and initialize new TSBs appropriately. Otherwise a zero
TAG looks "valid".
Make sure, for the window fixup cases, that we use the right
global registers and that we don't potentially trample on
the live global registers in etrap/rtrap handling (%g2 and
%g6) and that we put the missing virtual address properly
in %g5.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/ttable.h')
| -rw-r--r-- | include/asm-sparc64/ttable.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h index 9e28b240f3aa..2d5e3c464df5 100644 --- a/include/asm-sparc64/ttable.h +++ b/include/asm-sparc64/ttable.h | |||
| @@ -184,20 +184,20 @@ | |||
| 184 | ldxa [%g0] ASI_SCRATCHPAD, %g2; \ | 184 | ldxa [%g0] ASI_SCRATCHPAD, %g2; \ |
| 185 | ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \ | 185 | ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \ |
| 186 | ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \ | 186 | ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \ |
| 187 | srlx %g4, 22, %g7; \ | 187 | srlx %g4, 22, %g6; \ |
| 188 | sllx %g5, 48, %g6; \ | ||
| 189 | ba,pt %xcc, sun4v_itsb_miss; \ | 188 | ba,pt %xcc, sun4v_itsb_miss; \ |
| 190 | or %g6, %g7, %g6; \ | 189 | nop; \ |
| 190 | nop; \ | ||
| 191 | nop; | 191 | nop; |
| 192 | 192 | ||
| 193 | #define SUN4V_DTSB_MISS \ | 193 | #define SUN4V_DTSB_MISS \ |
| 194 | ldxa [%g0] ASI_SCRATCHPAD, %g2; \ | 194 | ldxa [%g0] ASI_SCRATCHPAD, %g2; \ |
| 195 | ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \ | 195 | ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \ |
| 196 | ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \ | 196 | ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \ |
| 197 | srlx %g4, 22, %g7; \ | 197 | srlx %g4, 22, %g6; \ |
| 198 | sllx %g5, 48, %g6; \ | ||
| 199 | ba,pt %xcc, sun4v_dtsb_miss; \ | 198 | ba,pt %xcc, sun4v_dtsb_miss; \ |
| 200 | or %g6, %g7, %g6; \ | 199 | nop; \ |
| 200 | nop; \ | ||
| 201 | nop; | 201 | nop; |
| 202 | 202 | ||
| 203 | /* Before touching these macros, you owe it to yourself to go and | 203 | /* Before touching these macros, you owe it to yourself to go and |