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authorDavid S. Miller <davem@davemloft.net>2006-01-31 21:32:44 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 04:11:21 -0500
commit4753eb2ac7022b999e5e484f1a5dc001dba22bd3 (patch)
tree138321ebd3b3c3aeb99517ec5158a65f556da774 /include/asm-sparc64/tsb.h
parent96c6e0d8e2a0eb1338751598be47fa1ffed91704 (diff)
[SPARC64]: Fix incorrect TSB lock bit handling.
The TSB_LOCK_BIT define is actually a special value shifted down by 32-bits for the assembler code macros. In C code, this isn't what we want. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/tsb.h')
-rw-r--r--include/asm-sparc64/tsb.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h
index 1f93b7d8cdbc..09ab3aaa8d20 100644
--- a/include/asm-sparc64/tsb.h
+++ b/include/asm-sparc64/tsb.h
@@ -47,13 +47,14 @@
47 * possible solution is to use RCU for the freeing of the TSB. 47 * possible solution is to use RCU for the freeing of the TSB.
48 */ 48 */
49 49
50#define TSB_TAG_LOCK (1 << (47 - 32)) 50#define TSB_TAG_LOCK_BIT 47
51#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
51 52
52#define TSB_MEMBAR membar #StoreStore 53#define TSB_MEMBAR membar #StoreStore
53 54
54#define TSB_LOCK_TAG(TSB, REG1, REG2) \ 55#define TSB_LOCK_TAG(TSB, REG1, REG2) \
5599: lduwa [TSB] ASI_N, REG1; \ 5699: lduwa [TSB] ASI_N, REG1; \
56 sethi %hi(TSB_TAG_LOCK), REG2;\ 57 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
57 andcc REG1, REG2, %g0; \ 58 andcc REG1, REG2, %g0; \
58 bne,pn %icc, 99b; \ 59 bne,pn %icc, 99b; \
59 nop; \ 60 nop; \