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authorDavid S. Miller <davem@sunset.davemloft.net>2007-03-16 20:20:28 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-03-16 20:20:28 -0400
commitd1acb4210aaa9bdc413d276dbc96d0a23ada97ba (patch)
treeb0ca2efd2b34e319aeb09c451d89fd1c9dc47ba3 /include/asm-sparc64/tsb.h
parentdb98e0b434a6265c451ffe94ec0a29b8d0aaf587 (diff)
[SPARC64]: Get DEBUG_PAGEALLOC working again.
We have to make sure to use base-pagesize TLB entries even during the early transition period where we need TLB miss handling but don't have the kernel page tables setup yet for the linear region. Also, it is necessary therefore to not use the 4MB TSB for these translations, and instead use the normal kernel TSB. This allows us to also get rid of the 4MB tsb for debug builds which shrinks the kernel a little bit. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/tsb.h')
-rw-r--r--include/asm-sparc64/tsb.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h
index e82612cd9f33..ab55ffcb7bf4 100644
--- a/include/asm-sparc64/tsb.h
+++ b/include/asm-sparc64/tsb.h
@@ -264,6 +264,7 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
264 be,a,pt %xcc, OK_LABEL; \ 264 be,a,pt %xcc, OK_LABEL; \
265 mov REG4, REG1; 265 mov REG4, REG1;
266 266
267#ifndef CONFIG_DEBUG_PAGEALLOC
267 /* This version uses a trick, the TAG is already (VADDR >> 22) so 268 /* This version uses a trick, the TAG is already (VADDR >> 22) so
268 * we can make use of that for the index computation. 269 * we can make use of that for the index computation.
269 */ 270 */
@@ -277,5 +278,6 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
277 cmp REG3, TAG; \ 278 cmp REG3, TAG; \
278 be,a,pt %xcc, OK_LABEL; \ 279 be,a,pt %xcc, OK_LABEL; \
279 mov REG4, REG1; 280 mov REG4, REG1;
281#endif
280 282
281#endif /* !(_SPARC64_TSB_H) */ 283#endif /* !(_SPARC64_TSB_H) */