[SPARC64]: Add PCI MSI support on Niagara.

This is kind of hokey, we could use the hardware provided facilities
much better.

MSIs are assosciated with MSI Queues.  MSI Queues generate interrupts
when any MSI assosciated with it is signalled.  This suggests a
two-tiered IRQ dispatch scheme:

	MSI Queue interrupt --> queue interrupt handler
		MSI dispatch --> driver interrupt handler

But we just get one-level under Linux currently.  What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.

So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.

We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available.  If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.

The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.

We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there.  This is
another ugly wart.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 28 insertions, 0 deletions

diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index dcfa7629358c..7a246d8a1828 100644
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -11,6 +11,7 @@
 #include <linux/pci.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
+#include <linux/msi.h>
 
 #include <asm/io.h>
 #include <asm/page.h>
@@ -177,6 +178,24 @@ struct pci_pbm_info {
         int                             is_66mhz_capable;
         int                             all_devs_66mhz;
 
+#ifdef CONFIG_PCI_MSI
+        /* MSI info.  */
+        u32                             msiq_num;
+        u32                             msiq_ent_count;
+        u32                             msiq_first;
+        u32                             msiq_first_devino;
+        u32                             msi_num;
+        u32                             msi_first;
+        u32                             msi_data_mask;
+        u32                             msix_data_width;
+        u64                             msi32_start;
+        u64                             msi64_start;
+        u32                             msi32_len;
+        u32                             msi64_len;
+        void                            *msi_queues;
+        unsigned long                   *msi_bitmap;
+#endif /* !(CONFIG_PCI_MSI) */
+
         /* This PBM's streaming buffer. */
         struct pci_strbuf               stc;
 
@@ -213,6 +232,12 @@ struct pci_controller_info {
         void (*base_address_update)(struct pci_dev *, int);
         void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
 
+#ifdef CONFIG_PCI_MSI
+        int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
+                             struct msi_desc *entry);
+        void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
+#endif
+
         /* Now things for the actual PCI bus probes. */
         struct pci_ops                  *pci_ops;
         unsigned int                    pci_first_busno;
@@ -231,6 +256,9 @@ struct pcidev_cookie {
         int num_prom_regs;
         struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
         int num_prom_assignments;
+#ifdef CONFIG_PCI_MSI
+        unsigned int                    msi_num;
+#endif
 };
 
 /* Currently these are the same across all PCI controllers