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authorDavid S. Miller <davem@davemloft.net>2006-02-23 17:19:28 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 04:14:00 -0500
commita0663a79ad4faebe1db4a56e2e767b120b12333a (patch)
tree612a53e387a6aea6116f8a1637050fa13c6d9f80 /include/asm-sparc64/mmu.h
parent074d82cf688fe2dfa7ba4a2317c56f62d13fb522 (diff)
[SPARC64]: Fix TLB context allocation with SMT style shared TLBs.
The context allocation scheme we use depends upon there being a 1<-->1 mapping from cpu to physical TLB for correctness. Chips like Niagara break this assumption. So what we do is notify all cpus with a cross call when the context version number changes, and if necessary this makes them allocate a valid context for the address space they are running at the time. Stress tested with make -j1024, make -j2048, and make -j4096 kernel builds on a 32-strand, 8 core, T2000 with 16GB of ram. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/mmu.h')
-rw-r--r--include/asm-sparc64/mmu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h
index 473d990848ee..1504d303a1d5 100644
--- a/include/asm-sparc64/mmu.h
+++ b/include/asm-sparc64/mmu.h
@@ -102,6 +102,7 @@ extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte
102extern void tsb_flush(unsigned long ent, unsigned long tag); 102extern void tsb_flush(unsigned long ent, unsigned long tag);
103 103
104typedef struct { 104typedef struct {
105 spinlock_t lock;
105 unsigned long sparc64_ctx_val; 106 unsigned long sparc64_ctx_val;
106 struct tsb *tsb; 107 struct tsb *tsb;
107 unsigned long tsb_rss_limit; 108 unsigned long tsb_rss_limit;