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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-01-09 14:18:33 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-01-09 14:18:33 -0500 |
| commit | 0a3a98f6dd4e8f4d928a09302c0d1c56f2192ac3 (patch) | |
| tree | 92f55e374a84d06ce8213a4540454760fdecf137 /include/asm-sparc64/cache.h | |
| parent | 8ef12c9f01afba47c2d33bb939085111ca0d0f7d (diff) | |
| parent | 5367f2d67c7d0bf1faae90e6e7b4e2ac3c9b5e0f (diff) | |
Merge Linus' tree.
Diffstat (limited to 'include/asm-sparc64/cache.h')
| -rw-r--r-- | include/asm-sparc64/cache.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h index ade5ec3bfd5a..f7d35a2ae9b8 100644 --- a/include/asm-sparc64/cache.h +++ b/include/asm-sparc64/cache.h | |||
| @@ -9,7 +9,6 @@ | |||
| 9 | #define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */ | 9 | #define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */ |
| 10 | 10 | ||
| 11 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) | 11 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) |
| 12 | #define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */ | ||
| 13 | 12 | ||
| 14 | #define SMP_CACHE_BYTES_SHIFT 6 | 13 | #define SMP_CACHE_BYTES_SHIFT 6 |
| 15 | #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */ | 14 | #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */ |