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authorIngo Molnar <mingo@elte.hu>2008-07-29 05:54:24 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-29 05:54:24 -0400
commit3825c9e8d01e4310c40a3903a354c433c32a7b6f (patch)
tree87c94a8076bbb38bd2cf20ab9bc23d6f74f6a0a8 /include/asm-sparc/viking.h
parent5d7b605245b1aa1a9cd6549b1f57d69273eb0c37 (diff)
parent6e86841d05f371b5b9b86ce76c02aaee83352298 (diff)
Merge commit 'v2.6.27-rc1' into x86/microcode
Conflicts: arch/x86/kernel/microcode.c Manual resolutions: arch/x86/kernel/microcode_amd.c arch/x86/kernel/microcode_intel.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-sparc/viking.h')
-rw-r--r--include/asm-sparc/viking.h253
1 files changed, 0 insertions, 253 deletions
diff --git a/include/asm-sparc/viking.h b/include/asm-sparc/viking.h
deleted file mode 100644
index 989930aeb093..000000000000
--- a/include/asm-sparc/viking.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * viking.h: Defines specific to the GNU/Viking MBUS module.
3 * This is SRMMU stuff.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7#ifndef _SPARC_VIKING_H
8#define _SPARC_VIKING_H
9
10#include <asm/asi.h>
11#include <asm/mxcc.h>
12#include <asm/pgtsrmmu.h>
13
14/* Bits in the SRMMU control register for GNU/Viking modules.
15 *
16 * -----------------------------------------------------------
17 * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
18 * -----------------------------------------------------------
19 * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
20 *
21 * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
22 * 1 = Twalks are cacheable in E-cache
23 *
24 * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
25 * and never caches them internally (or so states the docs). Therefore
26 * for machines lacking an E-cache (ie. in MBUS mode) this bit must
27 * remain cleared.
28 *
29 * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
30 * 1 = Passthru physical accesses cacheable
31 *
32 * This indicates whether accesses are cacheable when no cachable bit
33 * is present in the pte when the processor is in boot-mode or the
34 * access does not need pte's for translation (ie. pass-thru ASI's).
35 * "Cachable" is only referring to E-cache (if present) and not the
36 * on chip split I/D caches of the GNU/Viking.
37 *
38 * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
39 *
40 * This enables snooping on the GNU/Viking bus. This must be on
41 * for the hardware cache consistency mechanisms of the GNU/Viking
42 * to work at all. On non-mxcc GNU/Viking modules the split I/D
43 * caches will snoop regardless of whether they are enabled, this
44 * takes care of the case where the I or D or both caches are turned
45 * off yet still contain valid data. Note also that this bit does
46 * not affect GNU/Viking store-buffer snoops, those happen if the
47 * store-buffer is enabled no matter what.
48 *
49 * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
50 *
51 * This indicates whether the GNU/Viking is in boot-mode or not,
52 * if it is then all instruction fetch physical addresses are
53 * computed as 0xff0000000 + low 28 bits of requested address.
54 * GNU/Viking boot-mode does not affect data accesses. Also,
55 * in boot mode instruction accesses bypass the split on chip I/D
56 * caches, they may be cached by the GNU/MXCC if present and enabled.
57 *
58 * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
59 *
60 * This indicated the GNU/Viking configuration present. If in
61 * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
62 * not then the GNU/Viking is on a module VBUS connected directly
63 * to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
64 * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
65 *
66 * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
67 *
68 * The GNU/Viking store buffer allows the chip to continue execution
69 * after a store even if the data cannot be placed in one of the
70 * caches during that cycle. If disabled, all stores operations
71 * occur synchronously.
72 *
73 * IC: Instruction Cache -- 0 = off, 1 = on
74 * DC: Data Cache -- 0 = off, 1 = 0n
75 *
76 * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
77 * as mentioned above, these caches will snoop the bus in GNU/MBUS
78 * configurations even when disabled to avoid data corruption.
79 *
80 * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
81 * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
82 *
83 */
84
85#define VIKING_MMUENABLE 0x00000001
86#define VIKING_NOFAULT 0x00000002
87#define VIKING_PSO 0x00000080
88#define VIKING_DCENABLE 0x00000100 /* Enable data cache */
89#define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
90#define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
91#define VIKING_MMODE 0x00000800 /* MBUS mode */
92#define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
93#define VIKING_BMODE 0x00002000
94#define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
95#define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
96#define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
97#define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
98
99/*
100 * GNU/Viking Breakpoint Action Register fields.
101 */
102#define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
103
104/*
105 * GNU/Viking Cache Tags.
106 */
107#define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
108#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
109#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
110
111#ifndef __ASSEMBLY__
112
113static inline void viking_flush_icache(void)
114{
115 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
116 : /* no outputs */
117 : "i" (ASI_M_IC_FLCLEAR)
118 : "memory");
119}
120
121static inline void viking_flush_dcache(void)
122{
123 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
124 : /* no outputs */
125 : "i" (ASI_M_DC_FLCLEAR)
126 : "memory");
127}
128
129static inline void viking_unlock_icache(void)
130{
131 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
132 : /* no outputs */
133 : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
134 : "memory");
135}
136
137static inline void viking_unlock_dcache(void)
138{
139 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
140 : /* no outputs */
141 : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
142 : "memory");
143}
144
145static inline void viking_set_bpreg(unsigned long regval)
146{
147 __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
148 : /* no outputs */
149 : "r" (regval), "i" (ASI_M_ACTION)
150 : "memory");
151}
152
153static inline unsigned long viking_get_bpreg(void)
154{
155 unsigned long regval;
156
157 __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
158 : "=r" (regval)
159 : "i" (ASI_M_ACTION));
160 return regval;
161}
162
163static inline void viking_get_dcache_ptag(int set, int block,
164 unsigned long *data)
165{
166 unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
167 0x80000000;
168 unsigned long info, page;
169
170 __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
171 "or %%g0, %%g2, %0\n\t"
172 "or %%g0, %%g3, %1\n\t"
173 : "=r" (info), "=r" (page)
174 : "r" (ptag), "i" (ASI_M_DATAC_TAG)
175 : "g2", "g3");
176 data[0] = info;
177 data[1] = page;
178}
179
180static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
181 unsigned long *mxcc_cregp)
182{
183 unsigned long mreg = *mregp;
184 unsigned long mxcc_creg = *mxcc_cregp;
185
186 mreg &= ~(VIKING_PCENABLE);
187 mxcc_creg &= ~(MXCC_CTL_PARE);
188
189 __asm__ __volatile__ ("set 1f, %%g2\n\t"
190 "andcc %%g2, 4, %%g0\n\t"
191 "bne 2f\n\t"
192 " nop\n"
193 "1:\n\t"
194 "sta %0, [%%g0] %3\n\t"
195 "sta %1, [%2] %4\n\t"
196 "b 1f\n\t"
197 " nop\n\t"
198 "nop\n"
199 "2:\n\t"
200 "sta %0, [%%g0] %3\n\t"
201 "sta %1, [%2] %4\n"
202 "1:\n\t"
203 : /* no output */
204 : "r" (mreg), "r" (mxcc_creg),
205 "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
206 "i" (ASI_M_MXCC)
207 : "g2", "memory", "cc");
208 *mregp = mreg;
209 *mxcc_cregp = mxcc_creg;
210}
211
212static inline unsigned long viking_hwprobe(unsigned long vaddr)
213{
214 unsigned long val;
215
216 vaddr &= PAGE_MASK;
217 /* Probe all MMU entries. */
218 __asm__ __volatile__("lda [%1] %2, %0\n\t"
219 : "=r" (val)
220 : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
221 if (!val)
222 return 0;
223
224 /* Probe region. */
225 __asm__ __volatile__("lda [%1] %2, %0\n\t"
226 : "=r" (val)
227 : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
228 if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
229 vaddr &= ~SRMMU_PGDIR_MASK;
230 vaddr >>= PAGE_SHIFT;
231 return val | (vaddr << 8);
232 }
233
234 /* Probe segment. */
235 __asm__ __volatile__("lda [%1] %2, %0\n\t"
236 : "=r" (val)
237 : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
238 if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
239 vaddr &= ~SRMMU_REAL_PMD_MASK;
240 vaddr >>= PAGE_SHIFT;
241 return val | (vaddr << 8);
242 }
243
244 /* Probe page. */
245 __asm__ __volatile__("lda [%1] %2, %0\n\t"
246 : "=r" (val)
247 : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
248 return val;
249}
250
251#endif /* !__ASSEMBLY__ */
252
253#endif /* !(_SPARC_VIKING_H) */
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