diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-sparc/mbus.h |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-sparc/mbus.h')
-rw-r--r-- | include/asm-sparc/mbus.h | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/include/asm-sparc/mbus.h b/include/asm-sparc/mbus.h new file mode 100644 index 000000000000..5f2749015342 --- /dev/null +++ b/include/asm-sparc/mbus.h | |||
@@ -0,0 +1,102 @@ | |||
1 | /* $Id: mbus.h,v 1.9 1997/06/24 15:48:12 jj Exp $ | ||
2 | * mbus.h: Various defines for MBUS modules. | ||
3 | * | ||
4 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
5 | */ | ||
6 | |||
7 | #ifndef _SPARC_MBUS_H | ||
8 | #define _SPARC_MBUS_H | ||
9 | |||
10 | #include <asm/ross.h> /* HyperSparc stuff */ | ||
11 | #include <asm/cypress.h> /* Cypress Chips */ | ||
12 | #include <asm/viking.h> /* Ugh, bug city... */ | ||
13 | |||
14 | enum mbus_module { | ||
15 | HyperSparc = 0, | ||
16 | Cypress = 1, | ||
17 | Cypress_vE = 2, | ||
18 | Cypress_vD = 3, | ||
19 | Swift_ok = 4, | ||
20 | Swift_bad_c = 5, | ||
21 | Swift_lots_o_bugs = 6, | ||
22 | Tsunami = 7, | ||
23 | Viking_12 = 8, | ||
24 | Viking_2x = 9, | ||
25 | Viking_30 = 10, | ||
26 | Viking_35 = 11, | ||
27 | Viking_new = 12, | ||
28 | TurboSparc = 13, | ||
29 | SRMMU_INVAL_MOD = 14, | ||
30 | }; | ||
31 | |||
32 | extern enum mbus_module srmmu_modtype; | ||
33 | extern unsigned int viking_rev, swift_rev, cypress_rev; | ||
34 | |||
35 | /* HW Mbus module bugs we have to deal with */ | ||
36 | #define HWBUG_COPYBACK_BROKEN 0x00000001 | ||
37 | #define HWBUG_ASIFLUSH_BROKEN 0x00000002 | ||
38 | #define HWBUG_VACFLUSH_BITROT 0x00000004 | ||
39 | #define HWBUG_KERN_ACCBROKEN 0x00000008 | ||
40 | #define HWBUG_KERN_CBITBROKEN 0x00000010 | ||
41 | #define HWBUG_MODIFIED_BITROT 0x00000020 | ||
42 | #define HWBUG_PC_BADFAULT_ADDR 0x00000040 | ||
43 | #define HWBUG_SUPERSCALAR_BAD 0x00000080 | ||
44 | #define HWBUG_PACINIT_BITROT 0x00000100 | ||
45 | |||
46 | extern unsigned int hwbug_bitmask; | ||
47 | |||
48 | /* First the module type values. To find out which you have, just load | ||
49 | * the mmu control register from ASI_M_MMUREG alternate address space and | ||
50 | * shift the value right 28 bits. | ||
51 | */ | ||
52 | /* IMPL field means the company which produced the chip. */ | ||
53 | #define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */ | ||
54 | #define MBUS_LSI 0x3 /* LSI Logics */ | ||
55 | #define MBUS_ROSS 0x1 /* Ross is nice */ | ||
56 | #define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */ | ||
57 | |||
58 | /* Ross Module versions */ | ||
59 | #define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */ | ||
60 | #define ROSS_604_REV_F 0x1 /* revision f */ | ||
61 | #define ROSS_605 0xf /* revision a, a.1, and a.2 */ | ||
62 | #define ROSS_605_REV_B 0xe /* revision b */ | ||
63 | |||
64 | /* TI Viking Module versions */ | ||
65 | #define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */ | ||
66 | #define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */ | ||
67 | #define VIKING_REV_30 0x3 /* Version 3.0 */ | ||
68 | #define VIKING_REV_35 0x4 /* Version 3.5 */ | ||
69 | |||
70 | /* LSI Logics. */ | ||
71 | #define LSI_L64815 0x0 | ||
72 | |||
73 | /* Fujitsu */ | ||
74 | #define FMI_AURORA 0x4 /* MB8690x, a Swift module... */ | ||
75 | #define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */ | ||
76 | |||
77 | /* For multiprocessor support we need to be able to obtain the CPU id and | ||
78 | * the MBUS Module id. | ||
79 | */ | ||
80 | |||
81 | /* The CPU ID is encoded in the trap base register, 20 bits to the left of | ||
82 | * bit zero, with 2 bits being significant. | ||
83 | */ | ||
84 | #define TBR_ID_SHIFT 20 | ||
85 | |||
86 | extern __inline__ int get_cpuid(void) | ||
87 | { | ||
88 | register int retval; | ||
89 | __asm__ __volatile__("rd %%tbr, %0\n\t" | ||
90 | "srl %0, %1, %0\n\t" : | ||
91 | "=r" (retval) : | ||
92 | "i" (TBR_ID_SHIFT)); | ||
93 | return (retval & 3); | ||
94 | } | ||
95 | |||
96 | extern __inline__ int get_modid(void) | ||
97 | { | ||
98 | return (get_cpuid() | 0x8); | ||
99 | } | ||
100 | |||
101 | |||
102 | #endif /* !(_SPARC_MBUS_H) */ | ||